Commit f7f9abc5 authored by Marek Vasut's avatar Marek Vasut Committed by Vinod Koul
Browse files

phy: freescale: imx8m-pcie: Handle IMX8_PCIE_REFCLK_PAD_UNUSED 



The 'fsl,refclk-pad-mode' DT property used to select clock source for
PCIe PHY can have either of three values, IMX8_PCIE_REFCLK_PAD_INPUT,
IMX8_PCIE_REFCLK_PAD_OUTPUT, IMX8_PCIE_REFCLK_PAD_UNUSED. The first
two options are handled correctly by the driver, the last one is not,
this patch implements support for the last option.

The IMX8_PCIE_REFCLK_PAD_INPUT means PCIE_RESREF is PHY clock input,
the IMX8_PCIE_REFCLK_PAD_OUTPUT means PHY clock are sourced from SoC
internal PLL and output to PCIE_RESREF external IO pin. The last
IMX8_PCIE_REFCLK_PAD_UNUSED is a combination of previous two, PHY
clock are sourced from SoC internal PLL and not output anywhere.

Reviewed-by: default avatarRichard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
To: linux-phy@lists.infradead.org
Link: https://lore.kernel.org/r/20220413140710.10074-1-marex@denx.de


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 1599069a

drivers/phy/freescale/phy-fsl-imx8m-pcie.c

+8 −2
Original line number Diff line number Diff line
@@ -94,15 +94,21 @@ static int imx8_pcie_phy_init(struct phy *phy) 
			   IMX8MM_GPR_PCIE_CMN_RST);

	usleep_range(200, 500);



	if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT) {

	if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||

	    pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {

		/* Configure the pad as input */

		val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);

		writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN,

		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);

	} else if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) {

	} else {

		/* Configure the PHY to output the refclock via pad */

		writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN,

		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);

	}



	if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT ||

	    pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {

		/* Source clock from SoC internal PLL */

		writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,

		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);

		writel(AUX_PLL_REFCLK_SEL_SYS_PLL,