Commit f7d46c5e authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
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dt-bindings: display/msm: split qcom, mdss bindings



Split Mobile Display SubSystem (MDSS) root node bindings to the separate
yaml file. Changes to the existing (txt) schema:
 - Added optional "vbif_nrt_phys" region used by msm8996
 - Made "bus" and "vsync" clocks optional (they are not used by some
   platforms)
 - Added optional resets property referencing MDSS reset
 - Defined child nodes pointing to corresponding reference schema.
 - Dropped the "lut" clock. It was added to the schema by mistake (it is
   a part of mdp4 schema, not the mdss).

Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/508378/
Link: https://lore.kernel.org/r/20221024164225.3236654-2-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent fa0cf3e4
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@@ -2,37 +2,9 @@ Qualcomm adreno/snapdragon MDP5 display controller

Description:

This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
This is the bindings documentation for the MDP5 display
controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.

MDSS:
Required properties:
- compatible:
  * "qcom,mdss" - MDSS
- reg: Physical base address and length of the controller's registers.
- reg-names: The names of register regions. The following regions are required:
  * "mdss_phys"
  * "vbif_phys"
- interrupts: The interrupt signal from MDSS.
- interrupt-controller: identifies the node as an interrupt controller.
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
  source, should be 1.
- power-domains: a power domain consumer specifier according to
  Documentation/devicetree/bindings/power/power_domain.txt
- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required.
  * "iface"
  * "bus"
  * "vsync"
- #address-cells: number of address cells for the MDSS children. Should be 1.
- #size-cells: Should be 1.
- ranges: parent bus address space is the same as the child bus address space.

Optional properties:
- clock-names: the following clocks are optional:
  * "lut"

MDP5:
Required properties:
- compatible:
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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Mobile Display SubSystem (MDSS)

maintainers:
  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  - Rob Clark <robdclark@gmail.com>

description:
  This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
  encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.

properties:
  compatible:
    enum:
      - qcom,mdss

  reg:
    minItems: 2
    maxItems: 3

  reg-names:
    minItems: 2
    items:
      - const: mdss_phys
      - const: vbif_phys
      - const: vbif_nrt_phys

  interrupts:
    maxItems: 1

  interrupt-controller: true

  "#interrupt-cells":
    const: 1

  power-domains:
    maxItems: 1
    description: |
      The MDSS power domain provided by GCC

  clocks:
    minItems: 1
    items:
      - description: Display abh clock
      - description: Display axi clock
      - description: Display vsync clock

  clock-names:
    minItems: 1
    items:
      - const: iface
      - const: bus
      - const: vsync

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  ranges: true

  resets:
    items:
      - description: MDSS_CORE reset

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-controller
  - "#interrupt-cells"
  - power-domains
  - clocks
  - clock-names
  - "#address-cells"
  - "#size-cells"
  - ranges

patternProperties:
  "^mdp@[1-9a-f][0-9a-f]*$":
    type: object
    properties:
      compatible:
        const: qcom,mdp5

  "^dsi@[1-9a-f][0-9a-f]*$":
    type: object
    properties:
      compatible:
        const: qcom,mdss-dsi-ctrl

  "^phy@[1-9a-f][0-9a-f]*$":
    type: object
    properties:
      compatible:
        enum:
          - qcom,dsi-phy-14nm
          - qcom,dsi-phy-14nm-660
          - qcom,dsi-phy-14nm-8953
          - qcom,dsi-phy-20nm
          - qcom,dsi-phy-28nm-hpm
          - qcom,dsi-phy-28nm-lp

  "^hdmi-phy@[1-9a-f][0-9a-f]*$":
    type: object
    properties:
      compatible:
        enum:
          - qcom,hdmi-phy-8084
          - qcom,hdmi-phy-8660
          - qcom,hdmi-phy-8960
          - qcom,hdmi-phy-8974
          - qcom,hdmi-phy-8996

  "^hdmi-tx@[1-9a-f][0-9a-f]*$":
    type: object
    properties:
      compatible:
        enum:
          - qcom,hdmi-tx-8084
          - qcom,hdmi-tx-8660
          - qcom,hdmi-tx-8960
          - qcom,hdmi-tx-8974
          - qcom,hdmi-tx-8994
          - qcom,hdmi-tx-8996

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-msm8916.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    mdss@1a00000 {
        compatible = "qcom,mdss";
        reg = <0x1a00000 0x1000>,
              <0x1ac8000 0x3000>;
        reg-names = "mdss_phys", "vbif_phys";

        power-domains = <&gcc MDSS_GDSC>;

        clocks = <&gcc GCC_MDSS_AHB_CLK>,
                 <&gcc GCC_MDSS_AXI_CLK>,
                 <&gcc GCC_MDSS_VSYNC_CLK>;
        clock-names = "iface",
                      "bus",
                      "vsync";

        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-controller;
        #interrupt-cells = <1>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        mdp@1a01000 {
            compatible = "qcom,mdp5";
            reg = <0x01a01000 0x89000>;
            reg-names = "mdp_phys";

            interrupt-parent = <&mdss>;
            interrupts = <0>;

            clocks = <&gcc GCC_MDSS_AHB_CLK>,
                     <&gcc GCC_MDSS_AXI_CLK>,
                     <&gcc GCC_MDSS_MDP_CLK>,
                     <&gcc GCC_MDSS_VSYNC_CLK>;
            clock-names = "iface",
                      "bus",
                      "core",
                      "vsync";

            iommus = <&apps_iommu 4>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    mdp5_intf1_out: endpoint {
                        remote-endpoint = <&dsi0_in>;
                    };
                };
            };
        };
    };
...