Commit f73b836e authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.5-tag1' of... 

Merge tag 'renesas-clk-for-v6.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add PWM clock on Renesas R-Car V3U
 - Fix PLL5 on Renesas RZ/G2L and RZ/V2L

* tag 'renesas-clk-for-v6.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write
  clk: renesas: r8a779a0: Add PWM clock
parents ac9a7868 d1c20885

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -170,6 +170,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 
	DEF_MOD("msi3",		621,	R8A779A0_CLK_MSO),

	DEF_MOD("msi4",		622,	R8A779A0_CLK_MSO),

	DEF_MOD("msi5",		623,	R8A779A0_CLK_MSO),

	DEF_MOD("pwm0",		628,	R8A779A0_CLK_S1D8),

	DEF_MOD("rpc-if",	629,	R8A779A0_CLK_RPCD2),

	DEF_MOD("scif0",	702,	R8A779A0_CLK_S1D8),

	DEF_MOD("scif1",	703,	R8A779A0_CLK_S1D8),

drivers/clk/renesas/rzg2l-cpg.c

+2 −4
Original line number Diff line number Diff line
@@ -603,10 +603,8 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw, 
	}



	/* Output clock setting 1 */

	writel(CPG_SIPLL5_CLK1_POSTDIV1_WEN | CPG_SIPLL5_CLK1_POSTDIV2_WEN |

	       CPG_SIPLL5_CLK1_REFDIV_WEN  | (params.pl5_postdiv1 << 0) |

	       (params.pl5_postdiv2 << 4) | (params.pl5_refdiv << 8),

	       priv->base + CPG_SIPLL5_CLK1);

	writel((params.pl5_postdiv1 << 0) | (params.pl5_postdiv2 << 4) |

	       (params.pl5_refdiv << 8), priv->base + CPG_SIPLL5_CLK1);



	/* Output clock setting, SSCG modulation value setting 3 */

	writel((params.pl5_fracin << 8), priv->base + CPG_SIPLL5_CLK3);

drivers/clk/renesas/rzg2l-cpg.h

+0 −3
Original line number Diff line number Diff line
@@ -32,9 +32,6 @@ 
#define CPG_SIPLL5_STBY_RESETB_WEN	BIT(16)

#define CPG_SIPLL5_STBY_SSCG_EN_WEN	BIT(18)

#define CPG_SIPLL5_STBY_DOWNSPREAD_WEN	BIT(20)

#define CPG_SIPLL5_CLK1_POSTDIV1_WEN	BIT(16)

#define CPG_SIPLL5_CLK1_POSTDIV2_WEN	BIT(20)

#define CPG_SIPLL5_CLK1_REFDIV_WEN	BIT(24)

#define CPG_SIPLL5_CLK4_RESV_LSB	(0xFF)

#define CPG_SIPLL5_MON_PLL5_LOCK	BIT(4)