Commit d1c20885 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write 



As per the RZ/G2L HW(Rev.1.30 May2023) manual, there are no "write enable"
bits in the CPG_SIPLL5_CLK1 register.  So fix the CPG_SIPLL5_CLK register
write by removing the "write enable" bits.

Fixes: 1561380e ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support")
Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230518152334.514922-1-biju.das.jz@bp.renesas.com


[geert: Remove CPG_SIPLL5_CLK1_*_WEN bit definitions]
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 7f91fe3a

drivers/clk/renesas/rzg2l-cpg.c

+2 −4
Original line number Diff line number Diff line
@@ -603,10 +603,8 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw, 
	}



	/* Output clock setting 1 */

	writel(CPG_SIPLL5_CLK1_POSTDIV1_WEN | CPG_SIPLL5_CLK1_POSTDIV2_WEN |

	       CPG_SIPLL5_CLK1_REFDIV_WEN  | (params.pl5_postdiv1 << 0) |

	       (params.pl5_postdiv2 << 4) | (params.pl5_refdiv << 8),

	       priv->base + CPG_SIPLL5_CLK1);

	writel((params.pl5_postdiv1 << 0) | (params.pl5_postdiv2 << 4) |

	       (params.pl5_refdiv << 8), priv->base + CPG_SIPLL5_CLK1);



	/* Output clock setting, SSCG modulation value setting 3 */

	writel((params.pl5_fracin << 8), priv->base + CPG_SIPLL5_CLK3);

drivers/clk/renesas/rzg2l-cpg.h

+0 −3
Original line number Diff line number Diff line
@@ -32,9 +32,6 @@ 
#define CPG_SIPLL5_STBY_RESETB_WEN	BIT(16)

#define CPG_SIPLL5_STBY_SSCG_EN_WEN	BIT(18)

#define CPG_SIPLL5_STBY_DOWNSPREAD_WEN	BIT(20)

#define CPG_SIPLL5_CLK1_POSTDIV1_WEN	BIT(16)

#define CPG_SIPLL5_CLK1_POSTDIV2_WEN	BIT(20)

#define CPG_SIPLL5_CLK1_REFDIV_WEN	BIT(24)

#define CPG_SIPLL5_CLK4_RESV_LSB	(0xFF)

#define CPG_SIPLL5_MON_PLL5_LOCK	BIT(4)