Commit 7f91fe3a authored by Wolfram Sang's avatar Wolfram Sang Committed by Geert Uytterhoeven
Browse files

clk: renesas: r8a779a0: Add PWM clock 



Tested-by: default avatarKieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarKieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20230502170618.55967-2-wsa+renesas@sang-engineering.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent ac9a7868

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -170,6 +170,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 
	DEF_MOD("msi3",		621,	R8A779A0_CLK_MSO),

	DEF_MOD("msi4",		622,	R8A779A0_CLK_MSO),

	DEF_MOD("msi5",		623,	R8A779A0_CLK_MSO),

	DEF_MOD("pwm0",		628,	R8A779A0_CLK_S1D8),

	DEF_MOD("rpc-if",	629,	R8A779A0_CLK_RPCD2),

	DEF_MOD("scif0",	702,	R8A779A0_CLK_S1D8),

	DEF_MOD("scif1",	703,	R8A779A0_CLK_S1D8),