Commit f730f39e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-fixes-2021-02-18' of... 

Merge tag 'drm-intel-next-fixes-2021-02-18' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

- Restrict DRM_I915_DEBUG to developer builds (Chris)
- Fix return and error codes (Dan)
- Suspend/Resume fix (Chris)
- Disable atomics in L3 for gen9 (Chris)
- Flush before changing register state (Chris)
- Fix for GLK's HDMI (Ville)
- Fix ILK+'s plane strides with Xtiling (Ville)
- Correct surface base address for renderclear (Chris)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YC7uQY1kt6w0tRp+@intel.com
parents 4f8ad404 81ce8f04

drivers/gpu/drm/i915/Kconfig.debug

+2 −0
Original line number Diff line number Diff line
@@ -19,6 +19,8 @@ config DRM_I915_WERROR 
config DRM_I915_DEBUG

	bool "Enable additional driver debugging"

	depends on DRM_I915

	depends on EXPERT # only for developers

	depends on !COMPILE_TEST # never built by robots

	select DEBUG_FS

	select PREEMPT_COUNT

	select I2C_CHARDEV

drivers/gpu/drm/i915/display/i9xx_plane.c

+27 −0
Original line number Diff line number Diff line
@@ -255,6 +255,33 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) 
	else

		offset = 0;



	/*

	 * When using an X-tiled surface the plane starts to

	 * misbehave if the x offset + width exceeds the stride.

	 * hsw/bdw: underrun galore

	 * ilk/snb/ivb: wrap to the next tile row mid scanout

	 * i965/g4x: so far appear immune to this

	 * vlv/chv: TODO check

	 *

	 * Linear surfaces seem to work just fine, even on hsw/bdw

	 * despite them not using the linear offset anymore.

	 */

	if (INTEL_GEN(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) {

		u32 alignment = intel_surf_alignment(fb, 0);

		int cpp = fb->format->cpp[0];



		while ((src_x + src_w) * cpp > plane_state->color_plane[0].stride) {

			if (offset == 0) {

				drm_dbg_kms(&dev_priv->drm,

					    "Unable to find suitable display surface offset due to X-tiling\n");

				return -EINVAL;

			}



			offset = intel_plane_adjust_aligned_offset(&src_x, &src_y, plane_state, 0,

								   offset, offset - alignment);

		}

	}



	/*

	 * Put the final coordinates back so that the src

	 * coordinate checks will see the right values.

drivers/gpu/drm/i915/display/intel_display.c

+6 −6
Original line number Diff line number Diff line
@@ -1322,7 +1322,7 @@ static bool has_async_flips(struct drm_i915_private *i915) 
	return INTEL_GEN(i915) >= 5;

}



static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,

unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,

				  int color_plane)

{

	struct drm_i915_private *dev_priv = to_i915(fb->dev);
@@ -1590,7 +1590,7 @@ static u32 intel_adjust_aligned_offset(int *x, int *y, 
 * Adjust the tile offset by moving the difference into

 * the x/y offsets.

 */

static u32 intel_plane_adjust_aligned_offset(int *x, int *y,

u32 intel_plane_adjust_aligned_offset(int *x, int *y,

				      const struct intel_plane_state *state,

				      int color_plane,

				      u32 old_offset, u32 new_offset)

drivers/gpu/drm/i915/display/intel_display.h

+6 −0
Original line number Diff line number Diff line
@@ -653,6 +653,12 @@ void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state); 
struct intel_encoder *

intel_get_crtc_new_encoder(const struct intel_atomic_state *state,

			   const struct intel_crtc_state *crtc_state);

unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,

				  int color_plane);

u32 intel_plane_adjust_aligned_offset(int *x, int *y,

				      const struct intel_plane_state *state,

				      int color_plane,

				      u32 old_offset, u32 new_offset);



/* modesetting */

void intel_modeset_init_hw(struct drm_i915_private *i915);

drivers/gpu/drm/i915/display/intel_hdmi.c

+5 −1
Original line number Diff line number Diff line
@@ -2218,7 +2218,11 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, 
					  has_hdmi_sink))

		return MODE_CLOCK_HIGH;



	/* BXT DPLL can't generate 223-240 MHz */

	/* GLK DPLL can't generate 446-480 MHz */

	if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)

		return MODE_CLOCK_RANGE;



	/* BXT/GLK DPLL can't generate 223-240 MHz */

	if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)

		return MODE_CLOCK_RANGE;