Unverified Commit f71a6309 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!7521 v2 Avoiding false sharing in field access of tk_core 

Merge Pull Request from: @ci-robot 
 
PR sync from: Zheng Zengkai <zhengzengkai@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/5PMEB4JEANGB7W2Z53TX57TCN62X5BOU/ 
Backport patch from OLK-5.10 to stabilize the performance of unixbench
context1.

Wang ShaoBo (1):
  timekeeping: Avoiding false sharing in field access of tk_core

Zheng Zengkai (1):
  openeuler_defconfig: Enable CONFIG_ARCH_LLC_128_LINE_SIZE for
    Hisilicon platforms


-- 
2.20.1
 
https://gitee.com/openeuler/kernel/issues/I9PMP7 
 
Link:https://gitee.com/openeuler/kernel/pulls/7521

 

Reviewed-by: default avatarLiu Chao <liuchao173@huawei.com>
Reviewed-by: default avatarXie XiuQi <xiexiuqi@huawei.com>
Reviewed-by: default avatarZhang Jianhua <chris.zjh@huawei.com>
Reviewed-by: default avatarKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: default avatarZhang Peng <zhangpeng362@huawei.com>
parents 82db6dea 46b79917

arch/arm64/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -1606,6 +1606,15 @@ config HW_PERF_EVENTS 
	def_bool y

	depends on ARM_PMU



config ARCH_LLC_128_LINE_SIZE

	bool "Force 128 bytes alignment for fitting LLC cacheline"

	depends on ARCH_HISI

	default n

	help

	  As specific machine's LLC cacheline size may be up to

	  128 bytes, gaining performance improvement from fitting

	  128 Bytes LLC cache aligned.



# Supported by clang >= 7.0 or GCC >= 12.0.0

config CC_HAVE_SHADOW_CALL_STACK

	def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)

arch/arm64/configs/openeuler_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -477,6 +477,7 @@ CONFIG_HZ=250 
CONFIG_SCHED_HRTICK=y

CONFIG_ARCH_SPARSEMEM_ENABLE=y

CONFIG_HW_PERF_EVENTS=y

CONFIG_ARCH_LLC_128_LINE_SIZE=y

CONFIG_CC_HAVE_SHADOW_CALL_STACK=y

CONFIG_PARAVIRT=y

CONFIG_PARAVIRT_SCHED=y

arch/arm64/include/asm/cache.h

+6 −0
Original line number Diff line number Diff line
@@ -8,6 +8,12 @@ 
#define L1_CACHE_SHIFT		(6)

#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)



#ifdef CONFIG_ARCH_LLC_128_LINE_SIZE

#ifndef ____cacheline_aligned_128

#define ____cacheline_aligned_128  __attribute__((__aligned__(128)))

#endif

#endif



#define CLIDR_LOUU_SHIFT	27

#define CLIDR_LOC_SHIFT		24

#define CLIDR_LOUIS_SHIFT	21

kernel/time/timekeeping.c

+7 −0
Original line number Diff line number Diff line
@@ -48,9 +48,16 @@ DEFINE_RAW_SPINLOCK(timekeeper_lock); 
 * cache line.

 */

static struct {

#ifdef CONFIG_ARCH_LLC_128_LINE_SIZE

	u64		padding[8];

#endif

	seqcount_raw_spinlock_t	seq;

	struct timekeeper	timekeeper;

#ifdef CONFIG_ARCH_LLC_128_LINE_SIZE

} tk_core ____cacheline_aligned_128 = {

#else

} tk_core ____cacheline_aligned = {

#endif

	.seq = SEQCNT_RAW_SPINLOCK_ZERO(tk_core.seq, &timekeeper_lock),

};