Commit 46b79917 authored May 17, 2024 by Zheng Zengkai

openeuler_defconfig: Enable CONFIG_ARCH_LLC_128_LINE_SIZE for Hisilicon platforms

hulk inclusion
category: performance
bugzilla: https://gitee.com/openeuler/kernel/issues/I9PMP7


CVE: NA

---------------------------

On some Hisilicon platforms, like Kunpeng920, L3 cacheline size is
128 byte, enable CONFIG_ARCH_LLC_128_LINE_SIZE for these hisilicon
platforms by default.

Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>

parent d71becfc

arch/arm64/Kconfig

+2 −2

Original line number	Diff line number	Diff line
		@@ -1608,8 +1608,8 @@ config HW_PERF_EVENTS

		config ARCH_LLC_128_LINE_SIZE
		bool "Force 128 bytes alignment for fitting LLC cacheline"
		depends on ARM64
		default y
		depends on ARCH_HISI
		default n
		help
		As specific machine's LLC cacheline size may be up to
		128 bytes, gaining performance improvement from fitting

arch/arm64/configs/openeuler_defconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -477,6 +477,7 @@ CONFIG_HZ=250
		CONFIG_SCHED_HRTICK=y
		CONFIG_ARCH_SPARSEMEM_ENABLE=y
		CONFIG_HW_PERF_EVENTS=y
		CONFIG_ARCH_LLC_128_LINE_SIZE=y
		CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
		CONFIG_PARAVIRT=y
		CONFIG_PARAVIRT_SCHED=y