Commit f6d89dc5 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'mlxsw-Misc-updates' 



Ido Schimmel says:

====================
mlxsw: Misc updates

This patch set includes various updates for mlxsw.

Patches #1-#4 adjust the default burst size of packet trap policers to
conform to Spectrum-{2,3} requirements. The corresponding selftest is
also adjusted so that it could reliably pass on these platforms.

Patch #5 adjusts a selftest so that it could pass with both old and new
versions of mausezahn.

Patch #6 significantly reduces the runtime of tc-police scale test by
changing the preference and masks of the used tc filters.

Patch #7 prevents the driver from trying to set invalid ethtool link
modes.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 85eb5bc3 5bf01b57

drivers/net/ethernet/mellanox/mlxsw/reg.h

+0 −6
Original line number Diff line number Diff line
@@ -4174,7 +4174,6 @@ MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 


#define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M				BIT(0)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII			BIT(1)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII			BIT(2)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R				BIT(3)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G			BIT(4)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G		BIT(5)
@@ -4197,7 +4196,6 @@ MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 
#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4		BIT(2)

#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4		BIT(3)

#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR		BIT(4)

#define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2		BIT(5)

#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4		BIT(6)

#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4		BIT(7)

#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR		BIT(12)
@@ -4210,10 +4208,6 @@ MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 
#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4		BIT(20)

#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4		BIT(21)

#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4		BIT(22)

#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4	BIT(23)

#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX		BIT(24)

#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T		BIT(25)

#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T		BIT(26)

#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR		BIT(27)

#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR		BIT(28)

#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR		BIT(29)

drivers/net/ethernet/mellanox/mlxsw/spectrum_ethtool.c

+0 −38
Original line number Diff line number Diff line
@@ -992,22 +992,12 @@ struct mlxsw_sp1_port_link_mode { 
};



static const struct mlxsw_sp1_port_link_mode mlxsw_sp1_port_link_mode[] = {

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,

		.mask_ethtool	= ETHTOOL_LINK_MODE_100baseT_Full_BIT,

		.speed		= SPEED_100,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_SGMII |

				  MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,

		.mask_ethtool	= ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,

		.speed		= SPEED_1000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,

		.mask_ethtool	= ETHTOOL_LINK_MODE_10000baseT_Full_BIT,

		.speed		= SPEED_10000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |

				  MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
@@ -1022,11 +1012,6 @@ static const struct mlxsw_sp1_port_link_mode mlxsw_sp1_port_link_mode[] = { 
		.mask_ethtool	= ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,

		.speed		= SPEED_10000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,

		.mask_ethtool	= ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,

		.speed		= SPEED_20000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,

		.mask_ethtool	= ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
@@ -1092,11 +1077,6 @@ static const struct mlxsw_sp1_port_link_mode mlxsw_sp1_port_link_mode[] = { 
		.mask_ethtool	= ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,

		.speed		= SPEED_100000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,

		.mask_ethtool	= ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,

		.speed		= SPEED_100000,

	},

};



#define MLXSW_SP1_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp1_port_link_mode)
@@ -1236,14 +1216,6 @@ mlxsw_sp2_mask_ethtool_1000base_x_sgmii[] = { 
#define MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN \

	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_1000base_x_sgmii)



static const enum ethtool_link_mode_bit_indices

mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii[] = {

	ETHTOOL_LINK_MODE_2500baseX_Full_BIT,

};



#define MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN \

	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii)



static const enum ethtool_link_mode_bit_indices

mlxsw_sp2_mask_ethtool_5gbase_r[] = {

	ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
@@ -1407,16 +1379,6 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = { 
				  MLXSW_SP_PORT_MASK_WIDTH_8X,

		.speed		= SPEED_1000,

	},

	{

		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII,

		.mask_ethtool	= mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii,

		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN,

		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |

				  MLXSW_SP_PORT_MASK_WIDTH_2X |

				  MLXSW_SP_PORT_MASK_WIDTH_4X |

				  MLXSW_SP_PORT_MASK_WIDTH_8X,

		.speed		= SPEED_2500,

	},

	{

		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R,

		.mask_ethtool	= mlxsw_sp2_mask_ethtool_5gbase_r,

drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c

+11 −11
Original line number Diff line number Diff line
@@ -291,7 +291,7 @@ static void mlxsw_sp_rx_sample_listener(struct sk_buff *skb, u8 local_port, 
static const struct mlxsw_sp_trap_policer_item

mlxsw_sp_trap_policer_items_arr[] = {

	{

		.policer = MLXSW_SP_TRAP_POLICER(1, 10 * 1024, 128),

		.policer = MLXSW_SP_TRAP_POLICER(1, 10 * 1024, 4096),

	},

	{

		.policer = MLXSW_SP_TRAP_POLICER(2, 128, 128),
@@ -303,25 +303,25 @@ mlxsw_sp_trap_policer_items_arr[] = { 
		.policer = MLXSW_SP_TRAP_POLICER(4, 128, 128),

	},

	{

		.policer = MLXSW_SP_TRAP_POLICER(5, 16 * 1024, 128),

		.policer = MLXSW_SP_TRAP_POLICER(5, 16 * 1024, 8192),

	},

	{

		.policer = MLXSW_SP_TRAP_POLICER(6, 128, 128),

	},

	{

		.policer = MLXSW_SP_TRAP_POLICER(7, 1024, 128),

		.policer = MLXSW_SP_TRAP_POLICER(7, 1024, 512),

	},

	{

		.policer = MLXSW_SP_TRAP_POLICER(8, 20 * 1024, 1024),

		.policer = MLXSW_SP_TRAP_POLICER(8, 20 * 1024, 8192),

	},

	{

		.policer = MLXSW_SP_TRAP_POLICER(9, 128, 128),

	},

	{

		.policer = MLXSW_SP_TRAP_POLICER(10, 1024, 128),

		.policer = MLXSW_SP_TRAP_POLICER(10, 1024, 512),

	},

	{

		.policer = MLXSW_SP_TRAP_POLICER(11, 360, 128),

		.policer = MLXSW_SP_TRAP_POLICER(11, 256, 128),

	},

	{

		.policer = MLXSW_SP_TRAP_POLICER(12, 128, 128),
@@ -330,19 +330,19 @@ mlxsw_sp_trap_policer_items_arr[] = { 
		.policer = MLXSW_SP_TRAP_POLICER(13, 128, 128),

	},

	{

		.policer = MLXSW_SP_TRAP_POLICER(14, 1024, 128),

		.policer = MLXSW_SP_TRAP_POLICER(14, 1024, 512),

	},

	{

		.policer = MLXSW_SP_TRAP_POLICER(15, 1024, 128),

		.policer = MLXSW_SP_TRAP_POLICER(15, 1024, 512),

	},

	{

		.policer = MLXSW_SP_TRAP_POLICER(16, 24 * 1024, 4096),

		.policer = MLXSW_SP_TRAP_POLICER(16, 24 * 1024, 16384),

	},

	{

		.policer = MLXSW_SP_TRAP_POLICER(17, 19 * 1024, 4096),

		.policer = MLXSW_SP_TRAP_POLICER(17, 19 * 1024, 8192),

	},

	{

		.policer = MLXSW_SP_TRAP_POLICER(18, 1024, 128),

		.policer = MLXSW_SP_TRAP_POLICER(18, 1024, 512),

	},

	{

		.policer = MLXSW_SP_TRAP_POLICER(19, 1024, 512),

drivers/net/ethernet/mellanox/mlxsw/switchx2.c

+1 −24
Original line number Diff line number Diff line
@@ -550,16 +550,6 @@ struct mlxsw_sx_port_link_mode { 
};



static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,

		.supported	= SUPPORTED_100baseT_Full,

		.advertised	= ADVERTISED_100baseT_Full,

		.speed		= 100,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,

		.speed		= 100,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_SGMII |

				  MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
@@ -567,12 +557,6 @@ static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = { 
		.advertised	= ADVERTISED_1000baseKX_Full,

		.speed		= 1000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,

		.supported	= SUPPORTED_10000baseT_Full,

		.advertised	= ADVERTISED_10000baseT_Full,

		.speed		= 10000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |

				  MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
@@ -589,12 +573,6 @@ static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = { 
		.advertised	= ADVERTISED_10000baseKR_Full,

		.speed		= 10000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,

		.supported	= SUPPORTED_20000baseKR2_Full,

		.advertised	= ADVERTISED_20000baseKR2_Full,

		.speed		= 20000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,

		.supported	= SUPPORTED_40000baseCR4_Full,
@@ -634,8 +612,7 @@ static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = { 
	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |

				  MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |

				  MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |

				  MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,

				  MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,

		.speed		= 100000,

	},

};

tools/testing/selftests/drivers/net/mlxsw/devlink_trap_policer.sh

+5 −28
Original line number Diff line number Diff line
@@ -207,7 +207,7 @@ __rate_test() 


	RET=0



	devlink trap policer set $DEVLINK_DEV policer $id rate 1000 burst 16

	devlink trap policer set $DEVLINK_DEV policer $id rate 1000 burst 512

	devlink trap group set $DEVLINK_DEV group l3_drops policer $id



	# Send packets at highest possible rate and make sure they are dropped
@@ -220,8 +220,8 @@ __rate_test() 


	rate=$(trap_rate_get)

	pct=$((100 * (rate - 1000) / 1000))

	((-5 <= pct && pct <= 5))

	check_err $? "Expected rate 1000 pps, got $rate pps, which is $pct% off. Required accuracy is +-5%"

	((-10 <= pct && pct <= 10))

	check_err $? "Expected rate 1000 pps, got $rate pps, which is $pct% off. Required accuracy is +-10%"

	log_info "Expected rate 1000 pps, measured rate $rate pps"



	drop_rate=$(policer_drop_rate_get $id)
@@ -288,35 +288,12 @@ __burst_test() 


	RET=0



	devlink trap policer set $DEVLINK_DEV policer $id rate 1000 burst 32

	devlink trap policer set $DEVLINK_DEV policer $id rate 1000 burst 512

	devlink trap group set $DEVLINK_DEV group l3_drops policer $id



	# Send a burst of 64 packets and make sure that about 32 are received

	# and the rest are dropped by the policer

	log_info "=== Tx burst size: 64, Policer burst size: 32 pps ==="



	t0_rx=$(devlink_trap_rx_packets_get blackhole_route)

	t0_drop=$(devlink_trap_policer_rx_dropped_get $id)



	start_traffic $h1 192.0.2.1 198.51.100.100 $rp1_mac -c 64



	t1_rx=$(devlink_trap_rx_packets_get blackhole_route)

	t1_drop=$(devlink_trap_policer_rx_dropped_get $id)



	rx=$((t1_rx - t0_rx))

	pct=$((100 * (rx - 32) / 32))

	((-20 <= pct && pct <= 20))

	check_err $? "Expected burst size of 32 packets, got $rx packets, which is $pct% off. Required accuracy is +-20%"

	log_info "Expected burst size of 32 packets, measured burst size of $rx packets"



	drop=$((t1_drop - t0_drop))

	(( drop > 0 ))

	check_err $? "Expected non-zero policer drops, got 0"

	log_info "Measured policer drops of $drop packets"



	# Send a burst of 16 packets and make sure that 16 are received

	# and that none are dropped by the policer

	log_info "=== Tx burst size: 16, Policer burst size: 32 pps ==="

	log_info "=== Tx burst size: 16, Policer burst size: 512 ==="



	t0_rx=$(devlink_trap_rx_packets_get blackhole_route)

	t0_drop=$(devlink_trap_policer_rx_dropped_get $id)