Commit 5bf01b57 authored by Danielle Ratson's avatar Danielle Ratson Committed by David S. Miller
Browse files

mlxsw: spectrum_ethtool: Remove internal speeds from PTYS register 



The PTYS register is used to report and configure the port type and
speed. Currently, internal bits in the register are used the same way
other bits are used.

Using the internal bits can cause bad parameter firmware errors. For
example, trying to write to internal bit 25 returns:

EMAD reg access failed (tid=53e2bffa00004310,reg_id=5004(ptys),type=write,status=7(bad parameter))

Remove the internal bits from the PTYS register, so that it is no longer
possible to pass them to firmware.

Signed-off-by: default avatarDanielle Ratson <danieller@mellanox.com>
Reviewed-by: default avatarJiri Pirko <jiri@mellanox.com>
Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ffff9c9c

drivers/net/ethernet/mellanox/mlxsw/reg.h

+0 −6
Original line number Diff line number Diff line
@@ -4174,7 +4174,6 @@ MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 


#define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M				BIT(0)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII			BIT(1)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII			BIT(2)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R				BIT(3)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G			BIT(4)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G		BIT(5)
@@ -4197,7 +4196,6 @@ MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 
#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4		BIT(2)

#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4		BIT(3)

#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR		BIT(4)

#define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2		BIT(5)

#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4		BIT(6)

#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4		BIT(7)

#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR		BIT(12)
@@ -4210,10 +4208,6 @@ MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 
#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4		BIT(20)

#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4		BIT(21)

#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4		BIT(22)

#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4	BIT(23)

#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX		BIT(24)

#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T		BIT(25)

#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T		BIT(26)

#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR		BIT(27)

#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR		BIT(28)

#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR		BIT(29)

drivers/net/ethernet/mellanox/mlxsw/spectrum_ethtool.c

+0 −38
Original line number Diff line number Diff line
@@ -992,22 +992,12 @@ struct mlxsw_sp1_port_link_mode { 
};



static const struct mlxsw_sp1_port_link_mode mlxsw_sp1_port_link_mode[] = {

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,

		.mask_ethtool	= ETHTOOL_LINK_MODE_100baseT_Full_BIT,

		.speed		= SPEED_100,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_SGMII |

				  MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,

		.mask_ethtool	= ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,

		.speed		= SPEED_1000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,

		.mask_ethtool	= ETHTOOL_LINK_MODE_10000baseT_Full_BIT,

		.speed		= SPEED_10000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |

				  MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
@@ -1022,11 +1012,6 @@ static const struct mlxsw_sp1_port_link_mode mlxsw_sp1_port_link_mode[] = { 
		.mask_ethtool	= ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,

		.speed		= SPEED_10000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,

		.mask_ethtool	= ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,

		.speed		= SPEED_20000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,

		.mask_ethtool	= ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
@@ -1092,11 +1077,6 @@ static const struct mlxsw_sp1_port_link_mode mlxsw_sp1_port_link_mode[] = { 
		.mask_ethtool	= ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,

		.speed		= SPEED_100000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,

		.mask_ethtool	= ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,

		.speed		= SPEED_100000,

	},

};



#define MLXSW_SP1_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp1_port_link_mode)
@@ -1236,14 +1216,6 @@ mlxsw_sp2_mask_ethtool_1000base_x_sgmii[] = { 
#define MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN \

	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_1000base_x_sgmii)



static const enum ethtool_link_mode_bit_indices

mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii[] = {

	ETHTOOL_LINK_MODE_2500baseX_Full_BIT,

};



#define MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN \

	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii)



static const enum ethtool_link_mode_bit_indices

mlxsw_sp2_mask_ethtool_5gbase_r[] = {

	ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
@@ -1407,16 +1379,6 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = { 
				  MLXSW_SP_PORT_MASK_WIDTH_8X,

		.speed		= SPEED_1000,

	},

	{

		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII,

		.mask_ethtool	= mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii,

		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN,

		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |

				  MLXSW_SP_PORT_MASK_WIDTH_2X |

				  MLXSW_SP_PORT_MASK_WIDTH_4X |

				  MLXSW_SP_PORT_MASK_WIDTH_8X,

		.speed		= SPEED_2500,

	},

	{

		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R,

		.mask_ethtool	= mlxsw_sp2_mask_ethtool_5gbase_r,

drivers/net/ethernet/mellanox/mlxsw/switchx2.c

+1 −24
Original line number Diff line number Diff line
@@ -550,16 +550,6 @@ struct mlxsw_sx_port_link_mode { 
};



static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,

		.supported	= SUPPORTED_100baseT_Full,

		.advertised	= ADVERTISED_100baseT_Full,

		.speed		= 100,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,

		.speed		= 100,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_SGMII |

				  MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
@@ -567,12 +557,6 @@ static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = { 
		.advertised	= ADVERTISED_1000baseKX_Full,

		.speed		= 1000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,

		.supported	= SUPPORTED_10000baseT_Full,

		.advertised	= ADVERTISED_10000baseT_Full,

		.speed		= 10000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |

				  MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
@@ -589,12 +573,6 @@ static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = { 
		.advertised	= ADVERTISED_10000baseKR_Full,

		.speed		= 10000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,

		.supported	= SUPPORTED_20000baseKR2_Full,

		.advertised	= ADVERTISED_20000baseKR2_Full,

		.speed		= 20000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,

		.supported	= SUPPORTED_40000baseCR4_Full,
@@ -634,8 +612,7 @@ static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = { 
	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |

				  MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |

				  MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |

				  MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,

				  MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,

		.speed		= 100000,

	},

};