Commit f577c7c7 authored by Samson Tam's avatar Samson Tam Committed by Alex Deucher
Browse files

drm/amd/display: fix odm 2:1 policy not being applied consistently in 4k144 modes 



[Why]
odm 2:1 policy is splitting the pipes in 4k144.
then in subvp code, we merge the pipes. but since the
 configuration is unsupported, we keep the pipes split

[How]
for unsupported subvp configuration, redo the dml and
 pipe split calls

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarBrian Chang <Brian.Chang@amd.com>
Signed-off-by: default avatarSamson Tam <samson.tam@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d61e4ba3

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+5 −0
Original line number Diff line number Diff line
@@ -1082,6 +1082,11 @@ static void dcn32_full_validate_bw_helper(struct dc *dc, 
			dc->res_pool->funcs->remove_phantom_pipes(dc, context);

			vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported;

			*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);



			*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);

			/* This may adjust vlevel and maxMpcComb */

			if (*vlevel < context->bw_ctx.dml.soc.num_states)

				*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);

		} else {

			// only call dcn20_validate_apply_pipe_split_flags if we found a supported config

			memset(split, 0, MAX_PIPES * sizeof(int));