Commit d61e4ba3 authored by Derek Lai's avatar Derek Lai Committed by Alex Deucher
Browse files

drm/amd/display: do not change pipe split policy for RV2 



[Why]
RV2 do not change pipe split policy in the
minimal pipe split transition state.
This will unblock mode support on some
parts that limit to DPM0 for power reason.

[How]
Do not change pipe split policy in the
minimal pipe split transition state to
allow 4k multi display configs to be
supported at DPM0.

Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarBrian Chang <Brian.Chang@amd.com>
Signed-off-by: default avatarDerek Lai <Derek.Lai@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7930f58a

drivers/gpu/drm/amd/display/dc/core/dc.c

+6 −3
Original line number Diff line number Diff line
@@ -3546,8 +3546,10 @@ static bool commit_minimal_transition_state(struct dc *dc, 
	if (!transition_context)

		return false;



	if (!dc->config.is_vmin_only_asic) {

		tmp_policy = dc->debug.pipe_split_policy;

		dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;

	}



	dc_resource_state_copy_construct(transition_base_context, transition_context);
@@ -3573,6 +3575,7 @@ static bool commit_minimal_transition_state(struct dc *dc, 
	dc_release_state(transition_context);



	//restore previous pipe split policy

	if (!dc->config.is_vmin_only_asic)

		dc->debug.pipe_split_policy = tmp_policy;



	if (ret != DC_OK) {

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -401,6 +401,7 @@ struct dc_config { 
	uint8_t  vblank_alignment_max_frame_time_diff;

	bool is_asymmetric_memory;

	bool is_single_rank_dimm;

	bool is_vmin_only_asic;

	bool use_pipe_ctx_sync_logic;

	bool ignore_dpref_ss;

	bool enable_mipi_converter_optimization;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

+18 −0
Original line number Diff line number Diff line
@@ -1495,6 +1495,24 @@ static bool dcn10_resource_construct( 
	/* Other architectures we build for build this with soft-float */

	dcn10_resource_construct_fp(dc);



	if (!dc->config.is_vmin_only_asic)

		if (ASICREV_IS_RAVEN2(dc->ctx->asic_id.hw_internal_rev))

			switch (dc->ctx->asic_id.pci_revision_id) {

			case PRID_DALI_DE:

			case PRID_DALI_DF:

			case PRID_DALI_E3:

			case PRID_DALI_E4:

			case PRID_POLLOCK_94:

			case PRID_POLLOCK_95:

			case PRID_POLLOCK_E9:

			case PRID_POLLOCK_EA:

			case PRID_POLLOCK_EB:

				dc->config.is_vmin_only_asic = true;

				break;

			default:

				break;

			}



	pool->base.pp_smu = dcn10_pp_smu_create(ctx);



	/*

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

+6 −26
Original line number Diff line number Diff line
@@ -736,29 +736,12 @@ static void hack_bounding_box(struct dcn_bw_internal_vars *v, 
		hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);

}



static unsigned int get_highest_allowed_voltage_level(uint32_t chip_family,

						      uint32_t hw_internal_rev,

						      uint32_t pci_revision_id)

static unsigned int get_highest_allowed_voltage_level(bool is_vmin_only_asic)

{

	/* for low power RV2 variants, the highest voltage level we want is 0 */

	if ((chip_family == FAMILY_RV) &&

	     ASICREV_IS_RAVEN2(hw_internal_rev))

		switch (pci_revision_id) {

		case PRID_DALI_DE:

		case PRID_DALI_DF:

		case PRID_DALI_E3:

		case PRID_DALI_E4:

		case PRID_POLLOCK_94:

		case PRID_POLLOCK_95:

		case PRID_POLLOCK_E9:

		case PRID_POLLOCK_EA:

		case PRID_POLLOCK_EB:

	if (is_vmin_only_asic)

		return 0;

		default:

			break;

		}



	/* we are ok with all levels */

	else	/* we are ok with all levels */

		return 4;

}
@@ -1323,10 +1306,7 @@ bool dcn_validate_bandwidth( 
	PERFORMANCE_TRACE_END();

	BW_VAL_TRACE_FINISH();



	if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(

							dc->ctx->asic_id.chip_family,

							dc->ctx->asic_id.hw_internal_rev,

							dc->ctx->asic_id.pci_revision_id))

	if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->config.is_vmin_only_asic))

		return true;

	else

		return false;