arm64: tlb: Avoid synchronous TLBIs when freeing page tables

mainline inclusion
from mainline-4.20-rc1
commit: ace8cb75
category: feature
feature: Reduce synchronous TLB invalidation on ARM64
bugzilla: NA
CVE: NA

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By selecting HAVE_RCU_TABLE_INVALIDATE, we can rely on tlb_flush() being
called if we fail to batch table pages for freeing. This in turn allows
us to postpone walk-cache invalidation until tlb_finish_mmu(), which
avoids lots of unnecessary DSBs and means we can shoot down the ASID if
the range is large enough.

Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: Xuefeng Wang <wxf.wang@hisilicon.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>