Commit f300cb7f authored by Peng Fan's avatar Peng Fan Committed by Abel Vesa
Browse files

clk: imx: clk-fracn-gppll: correct rdiv 



According to Reference Manual:
 000b - Divide by 1
 001b - Divide by 1
 010b - Divide by 2
 011b - Divide by 3
 100b - Divide by 4
 101b - Divide by 5
 110b - Divide by 6
 111b - Divide by 7

So only need increase rdiv by 1 when the register value is 0.

Fixes: 1b26cb8a ("clk: imx: support fracn gppll")
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Reviewed-by: default avatarJacky Bai <ping.bai@nxp.com>
Reviewed-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20220609132902.3504651-7-peng.fan@oss.nxp.com


Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
parent 5ebaf9f7

drivers/clk/imx/clk-fracn-gppll.c

+2 −1
Original line number Diff line number Diff line
@@ -149,6 +149,7 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon 
	if (rate)

		return (unsigned long)rate;



	if (!rdiv)

		rdiv = rdiv + 1;



	switch (odiv) {