Commit 5ebaf9f7 authored Jun 09, 2022 by Liu Ying Committed by Abel Vesa Jun 16, 2022

clk: imx: clk-fracn-gppll: Return rate in rate table properly in ->recalc_rate()



The PLL parameters in rate table should be directly compared with
those read from PLL registers instead of the cooked ones.

Fixes: 1b26cb8a ("clk: imx: support fracn gppll")
Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20220609132902.3504651-6-peng.fan@oss.nxp.com


Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

parent 044034ef

drivers/clk/imx/clk-fracn-gppll.c

+13 −11

Original line number	Diff line number	Diff line
		@@ -131,18 +131,7 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon
		mfi = FIELD_GET(PLL_MFI_MASK, pll_div);

		rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
		rdiv = rdiv + 1;
		odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
		switch (odiv) {
		case 0:
		odiv = 2;
		break;
		case 1:
		odiv = 3;
		break;
		default:
		break;
		}

		/*
		* Sometimes, the recalculated rate has deviation due to
		@@ -160,6 +149,19 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon
		if (rate)
		return (unsigned long)rate;

		rdiv = rdiv + 1;

		switch (odiv) {
		case 0:
		odiv = 2;
		break;
		case 1:
		odiv = 3;
		break;
		default:
		break;
		}

		/* Fvco = Fref * (MFI + MFN / MFD) */
		fvco = fvco * mfi * mfd + fvco * mfn;
		do_div(fvco, mfd * rdiv * odiv);