Commit f21b807c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2021-06-11' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Another week of fixes, nothing too crazy, but a few all over the
  place.

  Two locking fixes in the core/ttm area, a couple of small driver fixes
  (radeon, sun4i, mcde, vc4). Then msm and amdgpu have a set of fixes
  each, mostly for smaller things, though the msm has a DSI fix for a
  black screen.

  I haven't seen any intel fixes this week so they may have a few that
  may or may not wait for next week.

  drm:
   - auth locking fix

  ttm:
   - locking fix

  amdgpu:
   - Use kvzmalloc in amdgu_bo_create
   - Use drm_dbg_kms for reporting failure to get a GEM FB
   - Fix some register offsets for Sienna Cichlid
   - Fix fall-through warning

  radeon:
   - memcpy_to/from_io fixes

  msm:
   - NULL ptr deref fix
   - CP_PROTECT reg programming fix
   - incorrect register shift fix
   - DSI blank screen fix

  sun4i:
   - hdmi output probing fix

  mcde:
   - DSI pipeline calc fix

  vc4:
   - out of bounds fix"

* tag 'drm-fixes-2021-06-11' of git://anongit.freedesktop.org/drm/drm:
  drm/msm/dsi: Stash away calculated vco frequency on recalc
  drm: Lock pointer access in drm_master_release()
  drm/mcde: Fix off by 10^3 in calculation
  drm/msm/a6xx: avoid shadow NULL reference in failure path
  drm/msm/a6xx: fix incorrectly set uavflagprd_inv field for A650
  drm/msm/a6xx: update/fix CP_PROTECT initialization
  radeon: use memcpy_to/fromio for UVD fw upload
  drm/amd/pm: Fix fall-through warning for Clang
  drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid
  drm/amdgpu: Use drm_dbg_kms for reporting failure to get a GEM FB
  drm/amdgpu: switch kzalloc to kvzalloc in amdgpu_bo_create
  drm/msm: Init mm_list before accessing it for use_vram path
  drm: Fix use-after-free read in drm_getunique()
  drm/vc4: fix vc4_atomic_commit_tail() logic
  drm/ttm: fix deref of bo->ttm without holding the lock v2
  drm/sun4i: dw-hdmi: Make HDMI PHY into a platform device
parents 929d931f 7de5c0d7

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

+2 −2
Original line number Diff line number Diff line
@@ -1057,7 +1057,7 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, 


	return 0;

err:

	drm_err(dev, "Failed to init gem fb: %d\n", ret);

	drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret);

	rfb->base.obj[0] = NULL;

	return ret;

}
@@ -1094,7 +1094,7 @@ int amdgpu_display_gem_fb_verify_and_init( 


	return 0;

err:

	drm_err(dev, "Failed to verify and init gem fb: %d\n", ret);

	drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);

	rfb->base.obj[0] = NULL;

	return ret;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

+2 −2
Original line number Diff line number Diff line
@@ -100,7 +100,7 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 
		kfree(ubo->metadata);

	}



	kfree(bo);

	kvfree(bo);

}



/**
@@ -552,7 +552,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, 
	BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo));



	*bo_ptr = NULL;

	bo = kzalloc(bp->bo_ptr_size, GFP_KERNEL);

	bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL);

	if (bo == NULL)

		return -ENOMEM;

	drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+21 −5
Original line number Diff line number Diff line
@@ -173,6 +173,9 @@ 
#define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030

#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0



#define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5

#define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1



#define GFX_RLCG_GC_WRITE_OLD	(0x8 << 28)

#define GFX_RLCG_GC_WRITE	(0x0 << 28)

#define GFX_RLCG_GC_READ	(0x1 << 28)
@@ -1480,8 +1483,15 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32 
		       (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;

	scratch_reg3 = adev->rmmio +

		       (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;



	if (adev->asic_type >= CHIP_SIENNA_CICHLID) {

		spare_int = adev->rmmio +

			    (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]

			     + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;

	} else {

		spare_int = adev->rmmio +

			    (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;

	}



	grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;

	grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
@@ -7349,9 +7359,15 @@ static int gfx_v10_0_hw_fini(void *handle) 
	if (amdgpu_sriov_vf(adev)) {

		gfx_v10_0_cp_gfx_enable(adev, false);

		/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */

		if (adev->asic_type >= CHIP_SIENNA_CICHLID) {

			tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);

			tmp &= 0xffffff00;

			WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);

		} else {

			tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);

			tmp &= 0xffffff00;

			WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);

		}



		return 0;

	}

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

+1 −0
Original line number Diff line number Diff line
@@ -810,6 +810,7 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 
		break;

	case AMD_DPM_FORCED_LEVEL_MANUAL:

		data->fine_grain_enabled = 1;

		break;

	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:

	default:

		break;

drivers/gpu/drm/drm_auth.c

+2 −1
Original line number Diff line number Diff line
@@ -314,9 +314,10 @@ int drm_master_open(struct drm_file *file_priv) 
void drm_master_release(struct drm_file *file_priv)

{

	struct drm_device *dev = file_priv->minor->dev;

	struct drm_master *master = file_priv->master;

	struct drm_master *master;



	mutex_lock(&dev->master_mutex);

	master = file_priv->master;

	if (file_priv->magic)

		idr_remove(&file_priv->master->magic_map, file_priv->magic);