Commit 7de5c0d7 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.13-2021-06-09' of... 

Merge tag 'amd-drm-fixes-5.13-2021-06-09' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-5.13-2021-06-09:

amdgpu:
- Use kvzmalloc in amdgu_bo_create
- Use drm_dbg_kms for reporting failure to get a GEM FB
- Fix some register offsets for Sienna Cichlid
- Fix fall-through warning

radeon:
- memcpy_to/from_io fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210610035631.3943-1-alexander.deucher@amd.com
parents 750643a9 ab8363d3

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

+2 −2
Original line number Diff line number Diff line
@@ -1057,7 +1057,7 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, 


	return 0;

err:

	drm_err(dev, "Failed to init gem fb: %d\n", ret);

	drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret);

	rfb->base.obj[0] = NULL;

	return ret;

}
@@ -1094,7 +1094,7 @@ int amdgpu_display_gem_fb_verify_and_init( 


	return 0;

err:

	drm_err(dev, "Failed to verify and init gem fb: %d\n", ret);

	drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);

	rfb->base.obj[0] = NULL;

	return ret;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

+2 −2
Original line number Diff line number Diff line
@@ -100,7 +100,7 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 
		kfree(ubo->metadata);

	}



	kfree(bo);

	kvfree(bo);

}



/**
@@ -552,7 +552,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, 
	BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo));



	*bo_ptr = NULL;

	bo = kzalloc(bp->bo_ptr_size, GFP_KERNEL);

	bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL);

	if (bo == NULL)

		return -ENOMEM;

	drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+21 −5
Original line number Diff line number Diff line
@@ -173,6 +173,9 @@ 
#define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030

#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0



#define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5

#define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1



#define GFX_RLCG_GC_WRITE_OLD	(0x8 << 28)

#define GFX_RLCG_GC_WRITE	(0x0 << 28)

#define GFX_RLCG_GC_READ	(0x1 << 28)
@@ -1480,8 +1483,15 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32 
		       (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;

	scratch_reg3 = adev->rmmio +

		       (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;



	if (adev->asic_type >= CHIP_SIENNA_CICHLID) {

		spare_int = adev->rmmio +

			    (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]

			     + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;

	} else {

		spare_int = adev->rmmio +

			    (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;

	}



	grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;

	grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
@@ -7349,9 +7359,15 @@ static int gfx_v10_0_hw_fini(void *handle) 
	if (amdgpu_sriov_vf(adev)) {

		gfx_v10_0_cp_gfx_enable(adev, false);

		/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */

		if (adev->asic_type >= CHIP_SIENNA_CICHLID) {

			tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);

			tmp &= 0xffffff00;

			WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);

		} else {

			tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);

			tmp &= 0xffffff00;

			WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);

		}



		return 0;

	}

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

+1 −0
Original line number Diff line number Diff line
@@ -810,6 +810,7 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 
		break;

	case AMD_DPM_FORCED_LEVEL_MANUAL:

		data->fine_grain_enabled = 1;

		break;

	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:

	default:

		break;

drivers/gpu/drm/radeon/radeon_uvd.c

+2 −2
Original line number Diff line number Diff line
@@ -286,7 +286,7 @@ int radeon_uvd_resume(struct radeon_device *rdev) 
	if (rdev->uvd.vcpu_bo == NULL)

		return -EINVAL;



	memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);

	memcpy_toio((void __iomem *)rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);



	size = radeon_bo_size(rdev->uvd.vcpu_bo);

	size -= rdev->uvd_fw->size;
@@ -294,7 +294,7 @@ int radeon_uvd_resume(struct radeon_device *rdev) 
	ptr = rdev->uvd.cpu_addr;

	ptr += rdev->uvd_fw->size;



	memset(ptr, 0, size);

	memset_io((void __iomem *)ptr, 0, size);



	return 0;

}