Commit f20b5913 authored by Carolina Jubran's avatar Carolina Jubran Committed by Wen Zhiwei
Browse files

net/mlx5: Add missing masks and QoS bit masks for scheduling elements 

stable inclusion
from stable-v6.6.52
commit fa2e98068d25edad55adda9ecad0a51f0b6faf28
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IAYXOD

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=fa2e98068d25edad55adda9ecad0a51f0b6faf28



--------------------------------

[ Upstream commit 452ef7f86036392005940de54228d42ca0044192 ]

Add the missing masks for supported element types and Transmit
Scheduling Arbiter (TSAR) types in scheduling elements.

Also, add the corresponding bit masks for these types in the QoS
capabilities of a NIC scheduler.

Fixes: 214baf22 ("net/mlx5e: Support HTB offload")
Signed-off-by: default avatarCarolina Jubran <cjubran@nvidia.com>
Reviewed-by: default avatarCosmin Ratiu <cratiu@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
Signed-off-by: default avatarWen Zhiwei <wenzhiwei@kylinos.cn>
parent 8ad82bc9

include/linux/mlx5/mlx5_ifc.h

+9 −1
Original line number Diff line number Diff line
@@ -1010,7 +1010,8 @@ struct mlx5_ifc_qos_cap_bits { 


	u8         max_tsar_bw_share[0x20];



	u8         reserved_at_100[0x20];

	u8         nic_element_type[0x10];

	u8         nic_tsar_type[0x10];



	u8         reserved_at_120[0x3];

	u8         log_meter_aso_granularity[0x5];
@@ -3847,6 +3848,7 @@ enum { 
	ELEMENT_TYPE_CAP_MASK_VPORT		= 1 << 1,

	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,

	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,

	ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP	= 1 << 4,

};



struct mlx5_ifc_scheduling_context_bits {
@@ -4546,6 +4548,12 @@ enum { 
	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,

};



enum {

	TSAR_TYPE_CAP_MASK_DWRR		= 1 << 0,

	TSAR_TYPE_CAP_MASK_ROUND_ROBIN	= 1 << 1,

	TSAR_TYPE_CAP_MASK_ETS		= 1 << 2,

};



struct mlx5_ifc_tsar_element_bits {

	u8         reserved_at_0[0x8];

	u8         tsar_type[0x8];