Commit 8ad82bc9 authored by Carolina Jubran's avatar Carolina Jubran Committed by Wen Zhiwei
Browse files

net/mlx5: Explicitly set scheduling element and TSAR type 

stable inclusion
from stable-v6.6.52
commit f015f63cc9c477d2f2cd2102ba1f3351be1a316d
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IAYXOD

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=f015f63cc9c477d2f2cd2102ba1f3351be1a316d



--------------------------------

[ Upstream commit c88146abe4d0f8cf659b2b8883fdc33936d2e3b8 ]

Ensure the scheduling element type and TSAR type are explicitly
initialized in the QoS rate group creation.

This prevents potential issues due to default values.

Fixes: 1ae258f8 ("net/mlx5: E-switch, Introduce rate limiting groups API")
Signed-off-by: default avatarCarolina Jubran <cjubran@nvidia.com>
Reviewed-by: default avatarCosmin Ratiu <cratiu@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
Signed-off-by: default avatarWen Zhiwei <wenzhiwei@kylinos.cn>
parent 6092ce02

drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c

+7 −0
Original line number Diff line number Diff line
@@ -420,6 +420,7 @@ __esw_qos_create_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *ex 
{

	u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {};

	struct mlx5_esw_rate_group *group;

	__be32 *attr;

	u32 divider;

	int err;
@@ -427,6 +428,12 @@ __esw_qos_create_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *ex 
	if (!group)

		return ERR_PTR(-ENOMEM);



	MLX5_SET(scheduling_context, tsar_ctx, element_type,

		 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR);



	attr = MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes);

	*attr = cpu_to_be32(TSAR_ELEMENT_TSAR_TYPE_DWRR << 16);



	MLX5_SET(scheduling_context, tsar_ctx, parent_element_id,

		 esw->qos.root_tsar_ix);

	err = mlx5_create_scheduling_element_cmd(esw->dev,