Commit f1697f36 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files

clk: qcom: camcc-sc7180: use parent_hws instead of parent_data 



If all parents are specified as clk_hw, we can use parent_hws instead of
parent_data.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-7-dmitry.baryshkov@linaro.org
parent 5d57a18f

drivers/clk/qcom/camcc-sc7180.c

+79 −77
Original line number Diff line number Diff line
@@ -126,7 +126,9 @@ static struct clk_fixed_factor cam_cc_pll2_out_early = { 
	.div = 2,

	.hw.init = &(struct clk_init_data){

		.name = "cam_cc_pll2_out_early",

		.parent_names = (const char *[]){ "cam_cc_pll2" },

		.parent_hws = (const struct clk_hw*[]){

			&cam_cc_pll2.clkr.hw,

		},

		.num_parents = 1,

		.ops = &clk_fixed_factor_ops,

	},
@@ -146,8 +148,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = { 
	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_pll2_out_aux",

		.parent_data = &(const struct clk_parent_data){

			.hw = &cam_cc_pll2.clkr.hw,

		.parent_hws = (const struct clk_hw*[]){

			&cam_cc_pll2.clkr.hw,

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,
@@ -729,8 +731,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_bps_ahb_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_slow_ahb_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -747,8 +749,8 @@ static struct clk_branch cam_cc_bps_areg_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_bps_areg_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_fast_ahb_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -778,8 +780,8 @@ static struct clk_branch cam_cc_bps_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_bps_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_bps_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_bps_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -809,8 +811,8 @@ static struct clk_branch cam_cc_cci_0_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_cci_0_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_cci_0_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_cci_0_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -827,8 +829,8 @@ static struct clk_branch cam_cc_cci_1_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_cci_1_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_cci_1_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_cci_1_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -845,8 +847,8 @@ static struct clk_branch cam_cc_core_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_core_ahb_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_slow_ahb_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -863,8 +865,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_cpas_ahb_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_slow_ahb_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -881,8 +883,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_csi0phytimer_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_csi0phytimer_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_csi0phytimer_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -899,8 +901,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_csi1phytimer_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_csi1phytimer_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_csi1phytimer_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -917,8 +919,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_csi2phytimer_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_csi2phytimer_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_csi2phytimer_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -935,8 +937,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_csi3phytimer_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_csi3phytimer_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_csi3phytimer_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -953,8 +955,8 @@ static struct clk_branch cam_cc_csiphy0_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_csiphy0_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_cphy_rx_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -971,8 +973,8 @@ static struct clk_branch cam_cc_csiphy1_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_csiphy1_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_cphy_rx_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -989,8 +991,8 @@ static struct clk_branch cam_cc_csiphy2_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_csiphy2_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_cphy_rx_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1007,8 +1009,8 @@ static struct clk_branch cam_cc_csiphy3_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_csiphy3_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_cphy_rx_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1025,8 +1027,8 @@ static struct clk_branch cam_cc_icp_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_icp_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_icp_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_icp_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1056,8 +1058,8 @@ static struct clk_branch cam_cc_ife_0_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_ife_0_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_ife_0_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_ife_0_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1074,8 +1076,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_ife_0_cphy_rx_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_cphy_rx_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1092,8 +1094,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_ife_0_csid_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_ife_0_csid_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_ife_0_csid_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1110,8 +1112,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_ife_0_dsp_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_ife_0_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_ife_0_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1141,8 +1143,8 @@ static struct clk_branch cam_cc_ife_1_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_ife_1_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_ife_1_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_ife_1_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1159,8 +1161,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_ife_1_cphy_rx_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_cphy_rx_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1177,8 +1179,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_ife_1_csid_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_ife_1_csid_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_ife_1_csid_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1195,8 +1197,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_ife_1_dsp_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_ife_1_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_ife_1_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1213,8 +1215,8 @@ static struct clk_branch cam_cc_ife_lite_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_ife_lite_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_ife_lite_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_ife_lite_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1231,8 +1233,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_ife_lite_cphy_rx_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_cphy_rx_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1249,8 +1251,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_ife_lite_csid_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_ife_lite_csid_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1267,8 +1269,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_ipe_0_ahb_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_slow_ahb_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1285,8 +1287,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_ipe_0_areg_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_fast_ahb_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1316,8 +1318,8 @@ static struct clk_branch cam_cc_ipe_0_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_ipe_0_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_ipe_0_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_ipe_0_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1334,8 +1336,8 @@ static struct clk_branch cam_cc_jpeg_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_jpeg_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_jpeg_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_jpeg_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1352,8 +1354,8 @@ static struct clk_branch cam_cc_lrme_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_lrme_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_lrme_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_lrme_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1370,8 +1372,8 @@ static struct clk_branch cam_cc_mclk0_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_mclk0_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_mclk0_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_mclk0_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1388,8 +1390,8 @@ static struct clk_branch cam_cc_mclk1_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_mclk1_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_mclk1_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_mclk1_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1406,8 +1408,8 @@ static struct clk_branch cam_cc_mclk2_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_mclk2_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_mclk2_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_mclk2_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1424,8 +1426,8 @@ static struct clk_branch cam_cc_mclk3_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_mclk3_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_mclk3_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_mclk3_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -1442,8 +1444,8 @@ static struct clk_branch cam_cc_mclk4_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_mclk4_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &cam_cc_mclk4_clk_src.clkr.hw,

			.parent_hws = (const struct clk_hw*[]){

				&cam_cc_mclk4_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,