Commit 5d57a18f authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files

clk: qcom: camcc-sc7180: get rid of the test clock 



The test clock isn't in the bindings and apparently it's not used by
anyone upstream.  Remove it.

Suggested-by: default avatarStephen Boyd <swboyd@chromium.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-6-dmitry.baryshkov@linaro.org
parent 3ca90171

drivers/clk/qcom/camcc-sc7180.c

+0 −15
Original line number Diff line number Diff line
@@ -29,7 +29,6 @@ enum { 
	P_CAM_CC_PLL2_OUT_AUX,

	P_CAM_CC_PLL2_OUT_EARLY,

	P_CAM_CC_PLL3_OUT_MAIN,

	P_CORE_BI_PLL_TEST_SE,

};



static const struct pll_vco agera_vco[] = {
@@ -187,26 +186,22 @@ static const struct parent_map cam_cc_parent_map_0[] = { 
	{ P_BI_TCXO, 0 },

	{ P_CAM_CC_PLL1_OUT_EVEN, 2 },

	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data cam_cc_parent_data_0[] = {

	{ .fw_name = "bi_tcxo" },

	{ .hw = &cam_cc_pll1.clkr.hw },

	{ .hw = &cam_cc_pll0.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};



static const struct parent_map cam_cc_parent_map_1[] = {

	{ P_BI_TCXO, 0 },

	{ P_CAM_CC_PLL2_OUT_AUX, 1 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data cam_cc_parent_data_1[] = {

	{ .fw_name = "bi_tcxo" },

	{ .hw = &cam_cc_pll2_out_aux.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};



static const struct parent_map cam_cc_parent_map_2[] = {
@@ -214,7 +209,6 @@ static const struct parent_map cam_cc_parent_map_2[] = { 
	{ P_CAM_CC_PLL2_OUT_EARLY, 4 },

	{ P_CAM_CC_PLL3_OUT_MAIN, 5 },

	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data cam_cc_parent_data_2[] = {
@@ -222,7 +216,6 @@ static const struct clk_parent_data cam_cc_parent_data_2[] = { 
	{ .hw = &cam_cc_pll2_out_early.hw },

	{ .hw = &cam_cc_pll3.clkr.hw },

	{ .hw = &cam_cc_pll0.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};



static const struct parent_map cam_cc_parent_map_3[] = {
@@ -231,7 +224,6 @@ static const struct parent_map cam_cc_parent_map_3[] = { 
	{ P_CAM_CC_PLL2_OUT_EARLY, 4 },

	{ P_CAM_CC_PLL3_OUT_MAIN, 5 },

	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data cam_cc_parent_data_3[] = {
@@ -240,33 +232,28 @@ static const struct clk_parent_data cam_cc_parent_data_3[] = { 
	{ .hw = &cam_cc_pll2_out_early.hw },

	{ .hw = &cam_cc_pll3.clkr.hw },

	{ .hw = &cam_cc_pll0.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};



static const struct parent_map cam_cc_parent_map_4[] = {

	{ P_BI_TCXO, 0 },

	{ P_CAM_CC_PLL3_OUT_MAIN, 5 },

	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data cam_cc_parent_data_4[] = {

	{ .fw_name = "bi_tcxo" },

	{ .hw = &cam_cc_pll3.clkr.hw },

	{ .hw = &cam_cc_pll0.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};



static const struct parent_map cam_cc_parent_map_5[] = {

	{ P_BI_TCXO, 0 },

	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data cam_cc_parent_data_5[] = {

	{ .fw_name = "bi_tcxo" },

	{ .hw = &cam_cc_pll0.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};



static const struct parent_map cam_cc_parent_map_6[] = {
@@ -274,7 +261,6 @@ static const struct parent_map cam_cc_parent_map_6[] = { 
	{ P_CAM_CC_PLL1_OUT_EVEN, 2 },

	{ P_CAM_CC_PLL3_OUT_MAIN, 5 },

	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data cam_cc_parent_data_6[] = {
@@ -282,7 +268,6 @@ static const struct clk_parent_data cam_cc_parent_data_6[] = { 
	{ .hw = &cam_cc_pll1.clkr.hw },

	{ .hw = &cam_cc_pll3.clkr.hw },

	{ .hw = &cam_cc_pll0.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};



static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {