Commit f0fe9f3c authored by Sandipan Das's avatar Sandipan Das Committed by Peter Zijlstra
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perf/x86/amd/uncore: Add PerfMonV2 RDPMC assignments 



The current RDPMC assignment scheme maps four DF PMCs and
six L3 PMCs from index 6 to 15.

If AMD Performance Monitoring Version 2 (PerfMonV2) is
supported, there may be additional DF counters available
which are mapped starting from index 16 i.e. just after
the L3 counters. Update the RDPMC assignments accordingly.

Signed-off-by: default avatarSandipan Das <sandipan.das@amd.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/1359379ef34da760f108b075ac138ab082caa3ba.1652954372.git.sandipan.das@amd.com
parent c390241a

arch/x86/events/amd/uncore.c

+10 −0
Original line number Diff line number Diff line
@@ -158,6 +158,16 @@ static int amd_uncore_add(struct perf_event *event, int flags) 
	hwc->event_base_rdpmc = uncore->rdpmc_base + hwc->idx;

	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;



	/*

	 * The first four DF counters are accessible via RDPMC index 6 to 9

	 * followed by the L3 counters from index 10 to 15. For processors

	 * with more than four DF counters, the DF RDPMC assignments become

	 * discontiguous as the additional counters are accessible starting

	 * from index 16.

	 */

	if (is_nb_event(event) && hwc->idx >= NUM_COUNTERS_NB)

		hwc->event_base_rdpmc += NUM_COUNTERS_L3;



	if (flags & PERF_EF_START)

		amd_uncore_start(event, PERF_EF_RELOAD);