Commit c390241a authored by Sandipan Das's avatar Sandipan Das Committed by Peter Zijlstra
Browse files

perf/x86/amd/uncore: Add PerfMonV2 DF event format 



If AMD Performance Monitoring Version 2 (PerfMonV2) is
supported, use bits 0-7, 32-37 as EventSelect and bits
8-15, 24-27 as UnitMask for Data Fabric (DF) events.

Signed-off-by: default avatarSandipan Das <sandipan.das@amd.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/ffc24d5a3375b1d6e457d88e83241114de5c1942.1652954372.git.sandipan.das@amd.com
parent 16b48c3f

arch/x86/events/amd/uncore.c

+17 −7
Original line number Diff line number Diff line
@@ -209,10 +209,14 @@ static int amd_uncore_event_init(struct perf_event *event) 
{

	struct amd_uncore *uncore;

	struct hw_perf_event *hwc = &event->hw;

	u64 event_mask = AMD64_RAW_EVENT_MASK_NB;



	if (event->attr.type != event->pmu->type)

		return -ENOENT;



	if (pmu_version >= 2 && is_nb_event(event))

		event_mask = AMD64_PERFMON_V2_RAW_EVENT_MASK_NB;



	/*

	 * NB and Last level cache counters (MSRs) are shared across all cores

	 * that share the same NB / Last level cache.  On family 16h and below,
@@ -221,7 +225,7 @@ static int amd_uncore_event_init(struct perf_event *event) 
	 * out. So we do not support sampling and per-thread events via

	 * CAP_NO_INTERRUPT, and we do not enable counter overflow interrupts:

	 */

	hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;

	hwc->config = event->attr.config & event_mask;

	hwc->idx = -1;



	if (event->cpu < 0)
@@ -300,8 +304,10 @@ static struct device_attribute format_attr_##_var = \ 


DEFINE_UNCORE_FORMAT_ATTR(event12,	event,		"config:0-7,32-35");

DEFINE_UNCORE_FORMAT_ATTR(event14,	event,		"config:0-7,32-35,59-60"); /* F17h+ DF */

DEFINE_UNCORE_FORMAT_ATTR(event14v2,	event,		"config:0-7,32-37");	   /* PerfMonV2 DF */

DEFINE_UNCORE_FORMAT_ATTR(event8,	event,		"config:0-7");		   /* F17h+ L3 */

DEFINE_UNCORE_FORMAT_ATTR(umask,	umask,		"config:8-15");

DEFINE_UNCORE_FORMAT_ATTR(umask8,	umask,		"config:8-15");

DEFINE_UNCORE_FORMAT_ATTR(umask12,	umask,		"config:8-15,24-27");	   /* PerfMonV2 DF */

DEFINE_UNCORE_FORMAT_ATTR(coreid,	coreid,		"config:42-44");	   /* F19h L3 */

DEFINE_UNCORE_FORMAT_ATTR(slicemask,	slicemask,	"config:48-51");	   /* F17h L3 */

DEFINE_UNCORE_FORMAT_ATTR(threadmask8,	threadmask,	"config:56-63");	   /* F17h L3 */
@@ -313,14 +319,14 @@ DEFINE_UNCORE_FORMAT_ATTR(sliceid, sliceid, "config:48-50"); /* F19h L3 */ 
/* Common DF and NB attributes */

static struct attribute *amd_uncore_df_format_attr[] = {

	&format_attr_event12.attr,	/* event */

	&format_attr_umask.attr,	/* umask */

	&format_attr_umask8.attr,	/* umask */

	NULL,

};



/* Common L2 and L3 attributes */

static struct attribute *amd_uncore_l3_format_attr[] = {

	&format_attr_event12.attr,	/* event */

	&format_attr_umask.attr,	/* umask */

	&format_attr_umask8.attr,	/* umask */

	NULL,				/* threadmask */

	NULL,

};
@@ -659,8 +665,12 @@ static int __init amd_uncore_init(void) 
	}



	if (boot_cpu_has(X86_FEATURE_PERFCTR_NB)) {

		if (boot_cpu_data.x86 >= 0x17)

		if (pmu_version >= 2) {

			*df_attr++ = &format_attr_event14v2.attr;

			*df_attr++ = &format_attr_umask12.attr;

		} else if (boot_cpu_data.x86 >= 0x17) {

			*df_attr = &format_attr_event14.attr;

		}



		amd_uncore_nb = alloc_percpu(struct amd_uncore *);

		if (!amd_uncore_nb) {
@@ -686,11 +696,11 @@ static int __init amd_uncore_init(void) 
	if (boot_cpu_has(X86_FEATURE_PERFCTR_LLC)) {

		if (boot_cpu_data.x86 >= 0x19) {

			*l3_attr++ = &format_attr_event8.attr;

			*l3_attr++ = &format_attr_umask.attr;

			*l3_attr++ = &format_attr_umask8.attr;

			*l3_attr++ = &format_attr_threadmask2.attr;

		} else if (boot_cpu_data.x86 >= 0x17) {

			*l3_attr++ = &format_attr_event8.attr;

			*l3_attr++ = &format_attr_umask.attr;

			*l3_attr++ = &format_attr_umask8.attr;

			*l3_attr++ = &format_attr_threadmask8.attr;

		}

arch/x86/include/asm/perf_event.h

+13 −0
Original line number Diff line number Diff line
@@ -89,6 +89,19 @@ 
#define AMD64_RAW_EVENT_MASK_NB		\

	(AMD64_EVENTSEL_EVENT        |  \

	 ARCH_PERFMON_EVENTSEL_UMASK)



#define AMD64_PERFMON_V2_EVENTSEL_EVENT_NB	\

	(AMD64_EVENTSEL_EVENT	|		\

	 GENMASK_ULL(37, 36))



#define AMD64_PERFMON_V2_EVENTSEL_UMASK_NB	\

	(ARCH_PERFMON_EVENTSEL_UMASK	|	\

	 GENMASK_ULL(27, 24))



#define AMD64_PERFMON_V2_RAW_EVENT_MASK_NB		\

	(AMD64_PERFMON_V2_EVENTSEL_EVENT_NB	|	\

	 AMD64_PERFMON_V2_EVENTSEL_UMASK_NB)



#define AMD64_NUM_COUNTERS				4

#define AMD64_NUM_COUNTERS_CORE				6

#define AMD64_NUM_COUNTERS_NB				4