Commit f0d4627f authored Jun 14, 2023 by Anshuman Khandual Committed by Catalin Marinas Jun 14, 2023

arm64/sysreg: Convert TRBIDR_EL1 register to automatic generation



This converts TRBIDR_EL1 register to automatic generation without
causing any functional change.

Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230614065949.146187-15-anshuman.khandual@arm.com


Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

parent a56035c9

arch/arm64/include/asm/sysreg.h

+0 −6

Original line number	Diff line number	Diff line
		@@ -227,14 +227,8 @@

		/* End of Statistical Profiling Extension */

		#define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)

		#define TRBSR_EL1_BSC_MASK GENMASK(5, 0)
		#define TRBSR_EL1_BSC_SHIFT 0
		#define TRBIDR_EL1_F BIT(5)
		#define TRBIDR_EL1_P BIT(4)
		#define TRBIDR_EL1_Align_MASK GENMASK(3, 0)
		#define TRBIDR_EL1_Align_SHIFT 0

		#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
		#define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)

arch/arm64/tools/sysreg

+13 −0

Original line number	Diff line number	Diff line
		@@ -2319,3 +2319,16 @@ Sysreg TRBTRG_EL1 3 0 9 11 6
		Res0 63:32
		Field 31:0 TRG
		EndSysreg

		Sysreg TRBIDR_EL1 3 0 9 11 7
		Res0 63:12
		Enum 11:8 EA
		0b0000 NON_DESC
		0b0001 IGNORE
		0b0010 SERROR
		EndEnum
		Res0 7:6
		Field 5 F
		Field 4 P
		Field 3:0 Align
		EndSysreg