Commit a56035c9 authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Catalin Marinas
Browse files

arm64/sysreg: Convert TRBTRG_EL1 register to automatic generation 



This converts TRBTRG_EL1 register to automatic generation without
causing any functional change.

Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230614065949.146187-14-anshuman.khandual@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 3077b1db

arch/arm64/include/asm/sysreg.h

+0 −3
Original line number Diff line number Diff line
@@ -227,13 +227,10 @@ 


/*** End of Statistical Profiling Extension ***/



#define SYS_TRBTRG_EL1			sys_reg(3, 0, 9, 11, 6)

#define SYS_TRBIDR_EL1			sys_reg(3, 0, 9, 11, 7)



#define TRBSR_EL1_BSC_MASK		GENMASK(5, 0)

#define TRBSR_EL1_BSC_SHIFT		0

#define TRBTRG_EL1_TRG_MASK		GENMASK(31, 0)

#define TRBTRG_EL1_TRG_SHIFT		0

#define TRBIDR_EL1_F			BIT(5)

#define TRBIDR_EL1_P			BIT(4)

#define TRBIDR_EL1_Align_MASK		GENMASK(3, 0)

arch/arm64/tools/sysreg

+5 −0
Original line number Diff line number Diff line
@@ -2314,3 +2314,8 @@ Enum 9:8 SH 
EndEnum

Field	7:0	Attr

EndSysreg



Sysreg	TRBTRG_EL1	3	0	9	11	6

Res0	63:32

Field	31:0	TRG

EndSysreg