Commit f0af26c8 authored by Jason Zeng's avatar Jason Zeng
Browse files

x86/cpu: fix kabi for cpuinfo_x86.vmx_capability 

Intel inclusion
category: feature
feature: IPI Virtualization
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5ODSC


CVE: N/A

-------------------------------------------------

The introduction of VMX tertiary features like IPI virtualization
causes the change of the size of struct cpu_info_x86. This patch
tries to put the tertiary features on a separate data structure.

Signed-off-by: default avatarJason Zeng <jason.zeng@intel.com>
parent c52cf141

arch/x86/include/asm/processor.h

+16 −0
Original line number Diff line number Diff line
@@ -142,6 +142,12 @@ struct cpuinfo_x86 { 
	unsigned		initialized : 1;

} __randomize_layout;



struct extra_cpuinfo_x86 {

#ifdef CONFIG_X86_VMX_FEATURE_NAMES

	__u32			vmx_tertiary_capability[NVMX_TERTIARY_INTS];

#endif

} __randomize_layout;



struct cpuid_regs {

	u32 eax, ebx, ecx, edx;

};
@@ -172,6 +178,8 @@ enum cpuid_regs_idx { 
extern struct cpuinfo_x86	boot_cpu_data;

extern struct cpuinfo_x86	new_cpu_data;



extern struct extra_cpuinfo_x86	extra_boot_cpu_data;



extern __u32			cpu_caps_cleared[NCAPINTS + NBUGINTS];

extern __u32			cpu_caps_set[NCAPINTS + NBUGINTS];
@@ -183,6 +191,14 @@ DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 
#define cpu_data(cpu)		boot_cpu_data

#endif



#ifdef CONFIG_SMP

DECLARE_PER_CPU_READ_MOSTLY(struct extra_cpuinfo_x86, extra_cpu_info);

#define extra_cpu_data(cpu)	per_cpu(extra_cpu_info, cpu)

#else

#define extra_cpu_info		extra_boot_cpu_data

#define extra_cpu_data(cpu)	extra_boot_cpu_data

#endif



extern const struct seq_operations cpuinfo_op;



#define cache_line_size()	(boot_cpu_data.x86_cache_alignment)

arch/x86/include/asm/vmx.h

+2 −1
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include <asm/vmxfeatures.h>



#define VMCS_CONTROL_BIT(x)	BIT(VMX_FEATURE_##x & 0x1f)

#define VMCS_TERTIARY_CONTROL_BIT(x)	BIT(VMX_TERTIARY_FEATURE_##x & 0x1f)



/*

 * Definitions of Primary Processor-Based VM-Execution Controls.
@@ -78,7 +79,7 @@ 
/*

 * Definitions of Tertiary Processor-Based VM-Execution Controls.

 */

#define TERTIARY_EXEC_IPI_VIRT			VMCS_CONTROL_BIT(IPI_VIRT)

#define TERTIARY_EXEC_IPI_VIRT			VMCS_TERTIARY_CONTROL_BIT(IPI_VIRT)



#define PIN_BASED_EXT_INTR_MASK                 VMCS_CONTROL_BIT(INTR_EXITING)

#define PIN_BASED_NMI_EXITING                   VMCS_CONTROL_BIT(NMI_EXITING)

arch/x86/include/asm/vmxfeatures.h

+3 −2
Original line number Diff line number Diff line
@@ -5,7 +5,8 @@ 
/*

 * Defines VMX CPU feature bits

 */

#define NVMXINTS			5 /* N 32-bit words worth of info */

#define NVMXINTS			3 /* N 32-bit words worth of info */

#define NVMX_TERTIARY_INTS		2 /* N 32-bit words worth of info */



/*

 * Note: If the comment begins with a quoted string, that string is used
@@ -86,5 +87,5 @@ 
#define VMX_FEATURE_ENCLV_EXITING	( 2*32+ 28) /* "" VM-Exit on ENCLV (leaf dependent) */



/* Tertiary Processor-Based VM-Execution Controls, word 3 */

#define VMX_FEATURE_IPI_VIRT		( 3*32+  4) /* Enable IPI virtualization */

#define VMX_TERTIARY_FEATURE_IPI_VIRT		( 3*32+  4) /* Enable IPI virtualization */

#endif /* _ASM_X86_VMXFEATURES_H */

arch/x86/kernel/cpu/common.c

+10 −0
Original line number Diff line number Diff line
@@ -1596,6 +1596,15 @@ static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 
#endif

}



#ifdef CONFIG_X86_VMX_FEATURE_NAMES

static void init_extra_cpu_data(u16 cpu_index)

{

	struct extra_cpuinfo_x86 *e = &extra_cpu_data(cpu_index);



	memset(&e->vmx_tertiary_capability, 0, sizeof(e->vmx_tertiary_capability));

}

#endif



/*

 * This does the hard work of actually picking apart the CPU stuff...

 */
@@ -1626,6 +1635,7 @@ static void identify_cpu(struct cpuinfo_x86 *c) 
	memset(&c->x86_capability, 0, sizeof(c->x86_capability));

#ifdef CONFIG_X86_VMX_FEATURE_NAMES

	memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));

	init_extra_cpu_data(c->cpu_index);

#endif



	generic_identify(c);

arch/x86/kernel/cpu/feat_ctl.c

+18 −7
Original line number Diff line number Diff line
@@ -15,16 +15,30 @@ enum vmx_feature_leafs { 
	MISC_FEATURES = 0,

	PRIMARY_CTLS,

	SECONDARY_CTLS,

	TERTIARY_CTLS_LOW,

	TERTIARY_CTLS_HIGH,

	NR_VMX_FEATURE_WORDS,

};



enum vmx_tertiary_feature_leafs {

	TERTIARY_CTLS_LOW = 0,

	TERTIARY_CTLS_HIGH,

};



#define VMX_F(x) BIT(VMX_FEATURE_##x & 0x1f)



static void init_vmx_tertiary_capabilities(u16 cpu_index)

{

	struct extra_cpuinfo_x86 *e = &extra_cpu_data(cpu_index);

	u32 low, high;



	/* All 64 bits of tertiary controls MSR are allowed-1 settings. */

	rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS3, &low, &high);

	e->vmx_tertiary_capability[TERTIARY_CTLS_LOW] = low;

	e->vmx_tertiary_capability[TERTIARY_CTLS_HIGH] = high;

}



static void init_vmx_capabilities(struct cpuinfo_x86 *c)

{

	u32 supported, funcs, ept, vpid, ign, low, high;

	u32 supported, funcs, ept, vpid, ign;



	BUILD_BUG_ON(NVMXINTS != NR_VMX_FEATURE_WORDS);
@@ -44,10 +58,7 @@ static void init_vmx_capabilities(struct cpuinfo_x86 *c) 
	rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &ign, &supported);

	c->vmx_capability[SECONDARY_CTLS] = supported;



	/* All 64 bits of tertiary controls MSR are allowed-1 settings. */

	rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS3, &low, &high);

	c->vmx_capability[TERTIARY_CTLS_LOW] = low;

	c->vmx_capability[TERTIARY_CTLS_HIGH] = high;

	init_vmx_tertiary_capabilities(c->cpu_index);



	rdmsr(MSR_IA32_VMX_PINBASED_CTLS, ign, supported);

	rdmsr_safe(MSR_IA32_VMX_VMFUNC, &ign, &funcs);