Commit f002488d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-5.18/parisc-3' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux 

Pull parisc architecture fixes from Helge Deller:
 "Some reverts of existing patches, which were necessary because of boot
  issues due to wrong CPU clock handling and cache issues which led to
  userspace segfaults with 32bit kernels. Dave has a whole bunch of
  upcoming cache fixes which I then plan to push in the next merge
  window.

  Other than that just small updates and fixes, e.g. defconfig updates,
  spelling fixes, a clocksource fix, boot topology fixes and a fix for
  /proc/cpuinfo output to satisfy lscpu"

* tag 'for-5.18/parisc-3' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
  Revert "parisc: Increase parisc_cache_flush_threshold setting"
  parisc: Mark cr16 clock unstable on all SMP machines
  parisc: Fix typos in comments
  parisc: Change MAX_ADDRESS to become unsigned long long
  parisc: Merge model and model name into one line in /proc/cpuinfo
  parisc: Re-enable GENERIC_CPU_DEVICES for !SMP
  parisc: Update 32- and 64-bit defconfigs
  parisc: Only list existing CPUs in cpu_possible_mask
  Revert "parisc: Fix patch code locking and flushing"
  Revert "parisc: Mark sched_clock unstable only if clocks are not syncronized"
  Revert "parisc: Mark cr16 CPU clocksource unstable on all SMP machines"
parents e3de3a1c ba0c0410

arch/parisc/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ config PARISC 
	select ARCH_HAVE_NMI_SAFE_CMPXCHG

	select GENERIC_SMP_IDLE_THREAD

	select GENERIC_ARCH_TOPOLOGY if SMP

	select GENERIC_CPU_DEVICES if !SMP

	select GENERIC_LIB_DEVMEM_IS_ALLOWED

	select SYSCTL_ARCH_UNALIGN_ALLOW

	select SYSCTL_EXCEPTION_TRACE

arch/parisc/configs/generic-32bit_defconfig

+3 −1
Original line number Diff line number Diff line
@@ -6,6 +6,9 @@ CONFIG_BSD_PROCESS_ACCT=y 
CONFIG_IKCONFIG=y

CONFIG_IKCONFIG_PROC=y

CONFIG_LOG_BUF_SHIFT=16

CONFIG_CGROUPS=y

CONFIG_NAMESPACES=y

CONFIG_USER_NS=y

CONFIG_BLK_DEV_INITRD=y

CONFIG_EXPERT=y

CONFIG_PERF_EVENTS=y
@@ -47,7 +50,6 @@ CONFIG_PARPORT=y 
CONFIG_PARPORT_PC=m

CONFIG_PARPORT_1284=y

CONFIG_BLK_DEV_LOOP=y

CONFIG_BLK_DEV_CRYPTOLOOP=y

CONFIG_BLK_DEV_RAM=y

CONFIG_BLK_DEV_RAM_SIZE=6144

CONFIG_BLK_DEV_SD=y

arch/parisc/configs/generic-64bit_defconfig

+2 −1
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ CONFIG_CGROUPS=y 
CONFIG_MEMCG=y

CONFIG_CGROUP_PIDS=y

CONFIG_CPUSETS=y

CONFIG_USER_NS=y

CONFIG_RELAY=y

CONFIG_BLK_DEV_INITRD=y

CONFIG_CC_OPTIMIZE_FOR_SIZE=y
@@ -267,9 +268,9 @@ CONFIG_CRYPTO_DEFLATE=m 
CONFIG_CRC_CCITT=m

CONFIG_LIBCRC32C=y

CONFIG_PRINTK_TIME=y

CONFIG_DEBUG_KERNEL=y

CONFIG_STRIP_ASM_SYMS=y

CONFIG_MAGIC_SYSRQ=y

CONFIG_DEBUG_FS=y

CONFIG_DEBUG_KERNEL=y

CONFIG_DEBUG_STACKOVERFLOW=y

# CONFIG_SCHED_DEBUG is not set

arch/parisc/include/asm/pgtable.h

+1 −1
Original line number Diff line number Diff line
@@ -160,7 +160,7 @@ extern void __update_cache(pte_t pte); 
#define SPACEID_SHIFT	(MAX_ADDRBITS - 32)

#else

#define MAX_ADDRBITS	(BITS_PER_LONG)

#define MAX_ADDRESS	(1UL << MAX_ADDRBITS)

#define MAX_ADDRESS	(1ULL << MAX_ADDRBITS)

#define SPACEID_SHIFT	0

#endif

arch/parisc/kernel/cache.c

+3 −15
Original line number Diff line number Diff line
@@ -403,7 +403,7 @@ void __init parisc_setup_cache_timing(void) 
{

	unsigned long rangetime, alltime;

	unsigned long size;

	unsigned long threshold, threshold2;

	unsigned long threshold;



	alltime = mfctl(16);

	flush_data_cache();
@@ -418,20 +418,8 @@ void __init parisc_setup_cache_timing(void) 
		alltime, size, rangetime);



	threshold = L1_CACHE_ALIGN(size * alltime / rangetime);



	/*

	 * The threshold computed above isn't very reliable since the

	 * flush times depend greatly on the percentage of dirty lines

	 * in the flush range. Further, the whole cache time doesn't

	 * include the time to refill lines that aren't in the mm/vma

	 * being flushed. By timing glibc build and checks on mako cpus,

	 * the following formula seems to work reasonably well. The

	 * value from the timing calculation is too small, and increases

	 * build and check times by almost a factor two.

	 */

	threshold2 = cache_info.dc_size * num_online_cpus();

	if (threshold2 > threshold)

		threshold = threshold2;

	if (threshold > cache_info.dc_size)

		threshold = cache_info.dc_size;

	if (threshold)

		parisc_cache_flush_threshold = threshold;

	printk(KERN_INFO "Cache flush threshold set to %lu KiB\n",