Commit eff0cb3d authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull pci updates from Bjorn Helgaas:
 "Enumeration:

   - Consolidate duplicated 'next function' scanning and extend to allow
     'isolated functions' on s390, similar to existing hypervisors
     (Niklas Schnelle)

  Resource management:
   - Implement pci_iobar_pfn() for sparc, which allows us to remove the
     sparc-specific pci_mmap_page_range() and pci_mmap_resource_range().

     This removes the ability to map the entire PCI I/O space using
     /proc/bus/pci, but we believe that's already been broken since
     v2.6.28 (Arnd Bergmann)

   - Move common PCI definitions to asm-generic/pci.h and rework others
     to be be more specific and more encapsulated in arches that need
     them (Stafford Horne)

  Power management:

   - Convert drivers to new *_PM_OPS macros to avoid need for '#ifdef
     CONFIG_PM_SLEEP' or '__maybe_unused' (Bjorn Helgaas)

  Virtualization:

   - Add ACS quirk for Broadcom BCM5750x multifunction NICs that isolate
     the functions but don't advertise an ACS capability (Pavan Chebbi)

  Error handling:

   - Clear PCI Status register during enumeration in case firmware left
     errors logged (Kai-Heng Feng)

   - When we have native control of AER, enable error reporting for all
     devices that support AER. Previously only a few drivers enabled
     this (Stefan Roese)

   - Keep AER error reporting enabled for switches. Previously we
     enabled this during enumeration but immediately disabled it (Stefan
     Roese)

   - Iterate over error counters instead of error strings to avoid
     printing junk in AER sysfs counters (Mohamed Khalfella)

  ASPM:

   - Remove pcie_aspm_pm_state_change() so ASPM config changes, e.g.,
     via sysfs, are not lost across power state changes (Kai-Heng Feng)

  Endpoint framework:

   - Don't stop an EPC when unbinding an EPF from it (Shunsuke Mie)

  Endpoint embedded DMA controller driver:

   - Simplify and clean up support for the DesignWare embedded DMA
     (eDMA) controller (Frank Li, Serge Semin)

  Broadcom STB PCIe controller driver:

   - Avoid config space accesses when link is down because we can't
     recover from the CPU aborts these cause (Jim Quinlan)

   - Look for power regulators described under Root Ports in DT and
     enable them before scanning the secondary bus (Jim Quinlan)

   - Disable/enable regulators in suspend/resume (Jim Quinlan)

  Freescale i.MX6 PCIe controller driver:

   - Simplify and clean up clock and PHY management (Richard Zhu)

   - Disable/enable regulators in suspend/resume (Richard Zhu)

   - Set PCIE_DBI_RO_WR_EN before writing DBI registers (Richard Zhu)

   - Allow speeds faster than Gen2 (Richard Zhu)

   - Make link being down a non-fatal error so controller probe doesn't
     fail if there are no Endpoints connected (Richard Zhu)

  Loongson PCIe controller driver:

   - Add ACPI and MCFG support for Loongson LS7A (Huacai Chen)

   - Avoid config reads to non-existent LS2K/LS7A devices because a
     hardware defect causes machine hangs (Huacai Chen)

   - Work around LS7A integrated devices that report incorrect Interrupt
     Pin values (Jianmin Lv)

  Marvell Aardvark PCIe controller driver:

   - Add support for AER and Slot capability on emulated bridge (Pali
     Rohár)

  MediaTek PCIe controller driver:

   - Add Airoha EN7532 to DT binding (John Crispin)

   - Allow building of driver for ARCH_AIROHA (Felix Fietkau)

  MediaTek PCIe Gen3 controller driver:

   - Print decoded LTSSM state when the link doesn't come up (Jianjun
     Wang)

  NVIDIA Tegra194 PCIe controller driver:

   - Convert DT binding to json-schema (Vidya Sagar)

   - Add DT bindings and driver support for Tegra234 Root Port and
     Endpoint mode (Vidya Sagar)

   - Fix some Root Port interrupt handling issues (Vidya Sagar)

   - Set default Max Payload Size to 256 bytes (Vidya Sagar)

   - Fix Data Link Feature capability programming (Vidya Sagar)

   - Extend Endpoint mode support to devices beyond Controller-5 (Vidya
     Sagar)

  Qualcomm PCIe controller driver:

   - Rework clock, reset, PHY power-on ordering to avoid hangs and
     improve consistency (Robert Marko, Christian Marangi)

   - Move pipe_clk handling to PHY drivers (Dmitry Baryshkov)

   - Add IPQ60xx support (Selvam Sathappan Periakaruppan)

   - Allow ASPM L1 and substates for 2.7.0 (Krishna chaitanya chundru)

   - Add support for more than 32 MSI interrupts (Dmitry Baryshkov)

  Renesas R-Car PCIe controller driver:

   - Convert DT binding to json-schema (Herve Codina)

   - Add Renesas RZ/N1D (R9A06G032) to rcar-gen2 DT binding and driver
     (Herve Codina)

  Samsung Exynos PCIe controller driver:

   - Fix phy-exynos-pcie driver so it follows the 'phy_init() before
     phy_power_on()' PHY programming model (Marek Szyprowski)

  Synopsys DesignWare PCIe controller driver:

   - Simplify and clean up the DWC core extensively (Serge Semin)

   - Fix an issue with programming the ATU for regions that cross a 4GB
     boundary (Serge Semin)

   - Enable the CDM check if 'snps,enable-cdm-check' exists; previously
     we skipped it if 'num-lanes' was absent (Serge Semin)

   - Allocate a 32-bit DMA-able page to be MSI target instead of using a
     driver data structure that may not be addressable with 32-bit
     address (Will McVicker)

   - Add DWC core support for more than 32 MSI interrupts (Dmitry
     Baryshkov)

  Xilinx Versal CPM PCIe controller driver:

   - Add DT binding and driver support for Versal CPM5 Gen5 Root Port
     (Bharat Kumar Gogada)"

* tag 'pci-v5.20-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (150 commits)
  PCI: imx6: Support more than Gen2 speed link mode
  PCI: imx6: Set PCIE_DBI_RO_WR_EN before writing DBI registers
  PCI: imx6: Reformat suspend callback to keep symmetric with resume
  PCI: imx6: Move the imx6_pcie_ltssm_disable() earlier
  PCI: imx6: Disable clocks in reverse order of enable
  PCI: imx6: Do not hide PHY driver callbacks and refine the error handling
  PCI: imx6: Reduce resume time by only starting link if it was up before suspend
  PCI: imx6: Mark the link down as non-fatal error
  PCI: imx6: Move regulator enable out of imx6_pcie_deassert_core_reset()
  PCI: imx6: Turn off regulator when system is in suspend mode
  PCI: imx6: Call host init function directly in resume
  PCI: imx6: Disable i.MX6QDL clock when disabling ref clocks
  PCI: imx6: Propagate .host_init() errors to caller
  PCI: imx6: Collect clock enables in imx6_pcie_clk_enable()
  PCI: imx6: Factor out ref clock disable to match enable
  PCI: imx6: Move imx6_pcie_clk_disable() earlier
  PCI: imx6: Move imx6_pcie_enable_ref_clk() earlier
  PCI: imx6: Move PHY management functions together
  PCI: imx6: Move imx6_pcie_grp_offset(), imx6_pcie_configure_type() earlier
  PCI: imx6: Convert to NOIRQ_SYSTEM_SLEEP_PM_OPS()
  ...
parents 31be1d0f c4f36c3a
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@@ -125,14 +125,14 @@ Following piece of code illustrates the usage of the SR-IOV API.
		...
	}

	static int dev_suspend(struct pci_dev *dev, pm_message_t state)
	static int dev_suspend(struct device *dev)
	{
		...

		return 0;
	}

	static int dev_resume(struct pci_dev *dev)
	static int dev_resume(struct device *dev)
	{
		...

@@ -165,8 +165,7 @@ Following piece of code illustrates the usage of the SR-IOV API.
		.id_table =	dev_id_table,
		.probe =	dev_probe,
		.remove =	dev_remove,
		.suspend =	dev_suspend,
		.resume =	dev_resume,
		.driver.pm =	&dev_pm_ops,
		.shutdown =	dev_shutdown,
		.sriov_configure = dev_sriov_configure,
	};
+1 −1
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@@ -125,7 +125,7 @@ implementation of that functionality. To support the historical interface of
mmap() through files in /proc/bus/pci, platforms may also set HAVE_PCI_MMAP.

Alternatively, platforms which set HAVE_PCI_MMAP may provide their own
implementation of pci_mmap_page_range() instead of defining
implementation of pci_mmap_resource_range() instead of defining
ARCH_GENERIC_PCI_MMAP_RESOURCE.

Platforms which support write-combining maps of PCI resources must define
+1 −0
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@@ -7,6 +7,7 @@ Required properties:
	"mediatek,mt7622-pcie"
	"mediatek,mt7623-pcie"
	"mediatek,mt7629-pcie"
	"airoha,en7523-pcie"
- device_type: Must be "pci"
- reg: Base addresses and lengths of the root ports.
- reg-names: Names of the above areas to use during resource lookup.
+319 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based)

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>
  - Vidya Sagar <vidyas@nvidia.com>

description: |
  This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
  inherits all the common properties defined in snps,dw-pcie-ep.yaml.  Some
  of the controller instances are dual mode; they can work either in Root
  Port mode or Endpoint mode but one at a time.

  On Tegra194, controllers C0, C4 and C5 support Endpoint mode.
  On Tegra234, controllers C5, C6, C7 and C10 support Endpoint mode.

  Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
  operate in the Endpoint mode because of the way the platform is designed.

properties:
  compatible:
    enum:
      - nvidia,tegra194-pcie-ep
      - nvidia,tegra234-pcie-ep

  reg:
    items:
      - description: controller's application logic registers
      - description: iATU and DMA registers. This is where the iATU (internal
          Address Translation Unit) registers of the PCIe core are made
          available for software access.
      - description: aperture where the Root Port's own configuration
          registers are available.
      - description: aperture used to map the remote Root Complex address space

  reg-names:
    items:
      - const: appl
      - const: atu_dma
      - const: dbi
      - const: addr_space

  interrupts:
    items:
      - description: controller interrupt

  interrupt-names:
    items:
      - const: intr

  clocks:
    items:
      - description: module clock

  clock-names:
    items:
      - const: core

  resets:
    items:
      - description: APB bus interface reset
      - description: module reset

  reset-names:
    items:
      - const: apb
      - const: core

  reset-gpios:
    description: Must contain a phandle to a GPIO controller followed by GPIO
      that is being used as PERST input signal. Please refer to pci.txt.

  phys:
    minItems: 1
    maxItems: 8

  phy-names:
    minItems: 1
    items:
      - const: p2u-0
      - const: p2u-1
      - const: p2u-2
      - const: p2u-3
      - const: p2u-4
      - const: p2u-5
      - const: p2u-6
      - const: p2u-7

  power-domains:
    maxItems: 1
    description: |
      A phandle to the node that controls power to the respective PCIe
      controller and a specifier name for the PCIe controller.

      Tegra194 specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h"
      Tegra234 specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h"

  interconnects:
    items:
      - description: memory read client
      - description: memory write client

  interconnect-names:
    items:
      - const: dma-mem # read
      - const: write

  dma-coherent: true

  nvidia,bpmp:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: |
      Must contain a pair of phandles to BPMP controller node followed by
      controller ID. Following are the controller IDs for each controller:

      Tegra194

        0: C0
        1: C1
        2: C2
        3: C3
        4: C4
        5: C5

      Tegra234

        0 : C0
        1 : C1
        2 : C2
        3 : C3
        4 : C4
        5 : C5
        6 : C6
        7 : C7
        8 : C8
        9 : C9
        10: C10

    items:
      - items:
          - description: phandle to BPMP controller node
          - description: PCIe controller ID
            maximum: 10

  nvidia,aspm-cmrt-us:
    description: Common Mode Restore Time for proper operation of ASPM to be
      specified in microseconds

  nvidia,aspm-pwr-on-t-us:
    description: Power On time for proper operation of ASPM to be specified in
      microseconds

  nvidia,aspm-l0s-entrance-latency-us:
    description: ASPM L0s entrance latency to be specified in microseconds

  vddio-pex-ctl-supply:
    description: A phandle to the regulator supply for PCIe side band signals

  nvidia,refclk-select-gpios:
    maxItems: 1
    description: GPIO used to enable REFCLK to controller from the host

  nvidia,enable-ext-refclk:
    description: |
      This boolean property needs to be present if the controller is configured
      to receive Reference Clock from the host.
      NOTE: This is applicable only for Tegra234.

    $ref: /schemas/types.yaml#/definitions/flag

  nvidia,enable-srns:
    description: |
      This boolean property needs to be present if the controller is
      configured to operate in SRNS (Separate Reference Clocks with No
      Spread-Spectrum Clocking).  NOTE: This is applicable only for
      Tegra234.

    $ref: /schemas/types.yaml#/definitions/flag

allOf:
  - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#

unevaluatedProperties: false

required:
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - resets
  - reset-names
  - power-domains
  - reset-gpios
  - vddio-pex-ctl-supply
  - num-lanes
  - phys
  - phy-names
  - nvidia,bpmp

examples:
  - |
    #include <dt-bindings/clock/tegra194-clock.h>
    #include <dt-bindings/gpio/tegra194-gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/tegra194-powergate.h>
    #include <dt-bindings/reset/tegra194-reset.h>

    bus@0 {
        #address-cells = <2>;
        #size-cells = <2>;
        ranges = <0x0 0x0 0x0 0x8 0x0>;

        pcie-ep@141a0000 {
            compatible = "nvidia,tegra194-pcie-ep";
            reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
                  <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
                  <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
                  <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
            reg-names = "appl", "atu_dma", "dbi", "addr_space";
            interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
            interrupt-names = "intr";

            clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
            clock-names = "core";

            resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
                     <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
            reset-names = "apb", "core";

            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
            pinctrl-names = "default";
            pinctrl-0 = <&clkreq_c5_bi_dir_state>;

            nvidia,bpmp = <&bpmp 5>;

            nvidia,aspm-cmrt-us = <60>;
            nvidia,aspm-pwr-on-t-us = <20>;
            nvidia,aspm-l0s-entrance-latency-us = <3>;

            vddio-pex-ctl-supply = <&vdd_1v8ao>;

            reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;

            nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
                                          GPIO_ACTIVE_HIGH>;

            num-lanes = <8>;

            phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
                   <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
                   <&p2u_nvhs_6>, <&p2u_nvhs_7>;

            phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
                        "p2u-5", "p2u-6", "p2u-7";
        };
    };

  - |
    #include <dt-bindings/clock/tegra234-clock.h>
    #include <dt-bindings/gpio/tegra234-gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/tegra234-powergate.h>
    #include <dt-bindings/reset/tegra234-reset.h>

    bus@0 {
        #address-cells = <2>;
        #size-cells = <2>;
        ranges = <0x0 0x0 0x0 0x8 0x0>;

        pcie-ep@141a0000 {
            compatible = "nvidia,tegra234-pcie-ep";
            power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
            reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
                  <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
                  <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
                  <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G)        */
            reg-names = "appl", "atu_dma", "dbi", "addr_space";

            interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
            interrupt-names = "intr";

            clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
            clock-names = "core";

            resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
                     <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
            reset-names = "apb", "core";

            nvidia,bpmp = <&bpmp 5>;

            nvidia,enable-ext-refclk;
            nvidia,aspm-cmrt-us = <60>;
            nvidia,aspm-pwr-on-t-us = <20>;
            nvidia,aspm-l0s-entrance-latency-us = <3>;

            vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>;

            reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;

            nvidia,refclk-select-gpios = <&gpio_aon
                                          TEGRA234_AON_GPIO(AA, 4)
                                          GPIO_ACTIVE_HIGH>;

            num-lanes = <8>;

            phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
                   <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
                   <&p2u_nvhs_6>, <&p2u_nvhs_7>;

            phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
                        "p2u-5", "p2u-6", "p2u-7";
        };
    };
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NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)

This PCIe controller is based on the Synopsis Designware PCIe IP
and thus inherits all the common properties defined in snps,dw-pcie.yaml and
snps,dw-pcie-ep.yaml.
Some of the controller instances are dual mode where in they can work either
in root port mode or endpoint mode but one at a time.

Required properties:
- power-domains: A phandle to the node that controls power to the respective
  PCIe controller and a specifier name for the PCIe controller. Following are
  the specifiers for the different PCIe controllers
    TEGRA194_POWER_DOMAIN_PCIEX8B: C0
    TEGRA194_POWER_DOMAIN_PCIEX1A: C1
    TEGRA194_POWER_DOMAIN_PCIEX1A: C2
    TEGRA194_POWER_DOMAIN_PCIEX1A: C3
    TEGRA194_POWER_DOMAIN_PCIEX4A: C4
    TEGRA194_POWER_DOMAIN_PCIEX8A: C5
  these specifiers are defined in
  "include/dt-bindings/power/tegra194-powergate.h" file.
- reg: A list of physical base address and length pairs for each set of
  controller registers. Must contain an entry for each entry in the reg-names
  property.
- reg-names: Must include the following entries:
  "appl": Controller's application logic registers
  "config": As per the definition in snps,dw-pcie.yaml
  "atu_dma": iATU and DMA registers. This is where the iATU (internal Address
             Translation Unit) registers of the PCIe core are made available
             for SW access.
  "dbi": The aperture where root port's own configuration registers are
         available
- interrupts: A list of interrupt outputs of the controller. Must contain an
  entry for each entry in the interrupt-names property.
- interrupt-names: Must include the following entries:
  "intr": The Tegra interrupt that is asserted for controller interrupts
- clocks: Must contain an entry for each entry in clock-names.
  See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
  - core
- resets: Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
  - apb
  - core
- phys: Must contain a phandle to P2U PHY for each entry in phy-names.
- phy-names: Must include an entry for each active lane.
  "p2u-N": where N ranges from 0 to one less than the total number of lanes
- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
  by controller-id. Following are the controller ids for each controller.
    0: C0
    1: C1
    2: C2
    3: C3
    4: C4
    5: C5
- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals

RC mode:
- compatible: Tegra19x must contain  "nvidia,tegra194-pcie"
- device_type: Must be "pci" for RC mode
- interrupt-names: Must include the following entries:
  "msi": The Tegra interrupt that is asserted when an MSI is received
- bus-range: Range of bus numbers associated with this controller
- #address-cells: Address representation for root ports (must be 3)
  - cell 0 specifies the bus and device numbers of the root port:
    [23:16]: bus number
    [15:11]: device number
  - cell 1 denotes the upper 32 address bits and should be 0
  - cell 2 contains the lower 32 address bits and is used to translate to the
    CPU address space
- #size-cells: Size representation for root ports (must be 2)
- ranges: Describes the translation of addresses for root ports and standard
  PCI regions. The entries must be 7 cells each, where the first three cells
  correspond to the address as described for the #address-cells property
  above, the fourth and fifth cells are for the physical CPU address to
  translate to and the sixth and seventh cells are as described for the
  #size-cells property above.
  - Entries setup the mapping for the standard I/O, memory and
    prefetchable PCI regions. The first cell determines the type of region
    that is setup:
    - 0x81000000: I/O memory region
    - 0x82000000: non-prefetchable memory region
    - 0xc2000000: prefetchable memory region
  Please refer to the standard PCI bus binding document for a more detailed
  explanation.
- #interrupt-cells: Size representation for interrupts (must be 1)
- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
  Please refer to the standard PCI bus binding document for a more detailed
  explanation.

EP mode:
In Tegra194, Only controllers C0, C4 & C5 support EP mode.
- compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep"
- reg-names: Must include the following entries:
  "addr_space": Used to map remote RC address space
- reset-gpios: Must contain a phandle to a GPIO controller followed by
  GPIO that is being used as PERST input signal. Please refer to pci.txt
  document.

Optional properties:
- pinctrl-names: A list of pinctrl state names.
  It is mandatory for C5 controller and optional for other controllers.
  - "default": Configures PCIe I/O for proper operation.
- pinctrl-0: phandle for the 'default' state of pin configuration.
  It is mandatory for C5 controller and optional for other controllers.
- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
- nvidia,update-fc-fixup: This is a boolean property and needs to be present to
    improve performance when a platform is designed in such a way that it
    satisfies at least one of the following conditions thereby enabling root
    port to exchange optimum number of FC (Flow Control) credits with
    downstream devices
    1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
    2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
       a) speed is Gen-2 and MPS is 256B
       b) speed is >= Gen-3 with any MPS
- nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM
   to be specified in microseconds
- nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be
   specified in microseconds
- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
   specified in microseconds

RC mode:
- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
  if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
  in p2972-0000 platform).
- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot
  if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
  in p2972-0000 platform).

EP mode:
- nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller
  followed by GPIO that is being used to enable REFCLK to controller from host

NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
operate in the endpoint mode because of the way the platform is designed.

Examples:
=========

Tegra194 RC mode:
-----------------

	pcie@14180000 {
		compatible = "nvidia,tegra194-pcie";
		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
		reg = <0x00 0x14180000 0x0 0x00020000   /* appl registers (128K)      */
		       0x00 0x38000000 0x0 0x00040000   /* configuration space (256K) */
		       0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K)  */
		reg-names = "appl", "config", "atu_dma";

		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		num-lanes = <8>;
		linux,pci-domain = <0>;

		pinctrl-names = "default";
		pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;

		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
		clock-names = "core";

		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
			 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
		reset-names = "apb", "core";

		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,	/* controller interrupt */
			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;	/* MSI interrupt */
		interrupt-names = "intr", "msi";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

		nvidia,bpmp = <&bpmp 0>;

		supports-clkreq;
		nvidia,aspm-cmrt-us = <60>;
		nvidia,aspm-pwr-on-t-us = <20>;
		nvidia,aspm-l0s-entrance-latency-us = <3>;

		bus-range = <0x0 0xff>;
		ranges = <0x81000000 0x0  0x38100000 0x0  0x38100000 0x0 0x00100000    /* downstream I/O (1MB) */
			  0x82000000 0x0  0x38200000 0x0  0x38200000 0x0 0x01E00000    /* non-prefetchable memory (30MB) */
			  0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>;  /* prefetchable memory (16GB) */

		vddio-pex-ctl-supply = <&vdd_1v8ao>;
		vpcie3v3-supply = <&vdd_3v3_pcie>;
		vpcie12v-supply = <&vdd_12v_pcie>;

		phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
		       <&p2u_hsio_5>;
		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
	};

Tegra194 EP mode:
-----------------

	pcie-ep@141a0000 {
		compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
		reg = <0x00 0x141a0000 0x0 0x00020000   /* appl registers (128K)      */
		       0x00 0x3a040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
		       0x00 0x3a080000 0x0 0x00040000   /* DBI reg space (256K)       */
		       0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
		reg-names = "appl", "atu_dma", "dbi", "addr_space";

		num-lanes = <8>;
		num-ib-windows = <2>;
		num-ob-windows = <8>;

		pinctrl-names = "default";
		pinctrl-0 = <&clkreq_c5_bi_dir_state>;

		clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
		clock-names = "core";

		resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
			 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
		reset-names = "apb", "core";

		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
		interrupt-names = "intr";

		nvidia,bpmp = <&bpmp 5>;

		nvidia,aspm-cmrt-us = <60>;
		nvidia,aspm-pwr-on-t-us = <20>;
		nvidia,aspm-l0s-entrance-latency-us = <3>;

		vddio-pex-ctl-supply = <&vdd_1v8ao>;

		reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;

		nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
					      GPIO_ACTIVE_HIGH>;

		phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
		       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
		       <&p2u_nvhs_6>, <&p2u_nvhs_7>;

		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
			    "p2u-5", "p2u-6", "p2u-7";
	};
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