Commit 31be1d0f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine 

Pull dmaengine updates from Vinod Koul:
 "New support / Core:

   - Remove DMA_MEMCPY_SG for lack of users

   - Tegra 234 dmaengine support

   - Mediatek MT8365 dma support

   - Apple ADMAC driver

  Updates:

   - Yaml conversion for ST-Ericsson DMA40 binding and Freescale edma

   - rz-dmac updates and device_synchronize support

   - Bunch of typo in comments fixes in drivers

   - multithread support in sf-pdma driver"

* tag 'dmaengine-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (50 commits)
  dmaengine: mediatek: mtk-hsdma: Fix typo 'the the' in comment
  dmaengine: axi-dmac: check cache coherency register
  dmaengine: sh: rz-dmac: Add device_synchronize callback
  dmaengine: sprd: Cleanup in .remove() after pm_runtime_get_sync() failed
  dmaengine: tegra: Add terminate() for Tegra234
  dt-bindings: dmaengine: Add compatible for Tegra234
  dmaengine: xilinx: use strscpy to replace strlcpy
  dmaengine: imx-sdma: Add FIFO stride support for multi FIFO script
  dmaengine: idxd: Correct IAX operation code names
  dmaengine: imx-dma: Cast of_device_get_match_data() with (uintptr_t)
  dmaengine: dw-axi-dmac: ignore interrupt if no descriptor
  dmaengine: dw-axi-dmac: do not print NULL LLI during error
  dmaengine: altera-msgdma: Fixed some inconsistent function name descriptions
  dmaengine: imx-sdma: Add missing struct documentation
  dmaengine: sf-pdma: Add multithread support for a DMA channel
  dt-bindings: dma: dw-axi-dmac: extend the number of interrupts
  dmaengine: dmatest: use strscpy to replace strlcpy
  dmaengine: ste_dma40: fix typo in comment
  dmaengine: jz4780: fix typo in comment
  dmaengine: s3c24xx: fix typo in comment
  ...
parents 36001a2f a1873f83

Documentation/devicetree/bindings/dma/apple,admac.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/apple,admac.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Apple Audio DMA Controller (ADMAC)



description: |

  Apple's Audio DMA Controller (ADMAC) is used to fetch and store audio samples

  on SoCs from the "Apple Silicon" family.



  The controller has been seen with up to 24 channels. Even-numbered channels

  are TX-only, odd-numbered are RX-only. Individual channels are coupled to

  fixed device endpoints.



maintainers:

  - Martin Povišer <povik+lin@cutebit.org>



allOf:

  - $ref: "dma-controller.yaml#"



properties:

  compatible:

    items:

      - enum:

          - apple,t6000-admac

          - apple,t8103-admac

      - const: apple,admac



  reg:

    maxItems: 1



  '#dma-cells':

    const: 1

    description:

      Clients specify a single cell with channel number.



  dma-channels:

    maximum: 24



  interrupts:

    minItems: 4

    maxItems: 4

    description:

      Interrupts that correspond to the 4 IRQ outputs of the controller. Usually

      only one of the controller outputs will be connected as an usable interrupt

      source. The remaining interrupts will be left without a valid value, e.g.

      in an interrupts-extended list the disconnected positions will contain

      an empty phandle reference <0>.



required:

  - compatible

  - reg

  - '#dma-cells'

  - dma-channels

  - interrupts



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/apple-aic.h>

    #include <dt-bindings/interrupt-controller/irq.h>



    aic: interrupt-controller {

      interrupt-controller;

      #interrupt-cells = <3>;

    };



    admac: dma-controller@238200000 {

      compatible = "apple,t8103-admac", "apple,admac";

      reg = <0x38200000 0x34000>;

      dma-channels = <24>;

      interrupts-extended = <0>,

                            <&aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>,

                            <0>,

                            <0>;

      #dma-cells = <1>;

    };

Documentation/devicetree/bindings/dma/fsl,edma.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/fsl,edma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale enhanced Direct Memory Access(eDMA) Controller



description: |

  The eDMA channels have multiplex capability by programmable

  memory-mapped registers. channels are split into two groups, called

  DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed

  by any channel of certain group, DMAMUX0 or DMAMUX1, but not both.



maintainers:

  - Peng Fan <peng.fan@nxp.com>



properties:

  compatible:

    oneOf:

      - enum:

          - fsl,vf610-edma

          - fsl,imx7ulp-edma

      - items:

          - const: fsl,ls1028a-edma

          - const: fsl,vf610-edma



  reg:

    minItems: 2

    maxItems: 3



  interrupts:

    minItems: 2

    maxItems: 17



  interrupt-names:

    minItems: 2

    maxItems: 17



  "#dma-cells":

    const: 2



  dma-channels:

    const: 32



  clocks:

    maxItems: 2



  clock-names:

    maxItems: 2



  big-endian:

    description: |

      If present registers and hardware scatter/gather descriptors of the

      eDMA are implemented in big endian mode, otherwise in little mode.

    type: boolean



required:

  - "#dma-cells"

  - compatible

  - reg

  - interrupts

  - clocks

  - dma-channels



allOf:

  - $ref: "dma-controller.yaml#"

  - if:

      properties:

        compatible:

          contains:

            const: fsl,vf610-edma

    then:

      properties:

        clock-names:

          items:

            - const: dmamux0

            - const: dmamux1

        interrupts:

          maxItems: 2

        interrupt-names:

          items:

            - const: edma-tx

            - const: edma-err

        reg:

          maxItems: 3



  - if:

      properties:

        compatible:

          contains:

            const: fsl,imx7ulp-edma

    then:

      properties:

        clock-names:

          items:

            - const: dma

            - const: dmamux0

        interrupts:

          maxItems: 17

        reg:

          maxItems: 2



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/vf610-clock.h>



    edma0: dma-controller@40018000 {

      #dma-cells = <2>;

      compatible = "fsl,vf610-edma";

      reg = <0x40018000 0x2000>,

            <0x40024000 0x1000>,

            <0x40025000 0x1000>;

      interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,

                   <0 9 IRQ_TYPE_LEVEL_HIGH>;

      interrupt-names = "edma-tx", "edma-err";

      dma-channels = <32>;

      clock-names = "dmamux0", "dmamux1";

      clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>;

    };



  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/imx7ulp-clock.h>



    edma1: dma-controller@40080000 {

      #dma-cells = <2>;

      compatible = "fsl,imx7ulp-edma";

      reg = <0x40080000 0x2000>,

            <0x40210000 0x1000>;

      dma-channels = <32>;

      interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,

                   /* last is eDMA2-ERR interrupt */

                   <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

       clock-names = "dma", "dmamux0";

       clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>;

    };

Documentation/devicetree/bindings/dma/fsl-edma.txt

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* Freescale enhanced Direct Memory Access(eDMA) Controller



  The eDMA channels have multiplex capability by programmble memory-mapped

registers. channels are split into two groups, called DMAMUX0 and DMAMUX1,

specific DMA request source can only be multiplexed by any channel of certain

group, DMAMUX0 or DMAMUX1, but not both.



* eDMA Controller

Required properties:

- compatible :

	- "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC

	- "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp

	- "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the

	  LS1028A SoC.

- reg : Specifies base physical address(s) and size of the eDMA registers.

	The 1st region is eDMA control register's address and size.

	The 2nd and the 3rd regions are programmable channel multiplexing

	control register's address and size.

- interrupts : A list of interrupt-specifiers, one for each entry in

	interrupt-names on vf610 similar SoC. But for i.mx7ulp per channel

	per transmission interrupt, total 16 channel interrupt and 1

	error interrupt(located in the last), no interrupt-names list on

	i.mx7ulp for clean on dts.

- #dma-cells : Must be <2>.

	The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1).

	Specific request source can only be multiplexed by specific channels

	group called DMAMUX.

	The 2nd cell specifies the request source(slot) ID.

	See the SoC's reference manual for all the supported request sources.

- dma-channels : Number of channels supported by the controller

- clock-names : A list of channel group clock names. Should contain:

	"dmamux0" - clock name of mux0 group

	"dmamux1" - clock name of mux1 group

	Note: No dmamux0 on i.mx7ulp, but another 'dma' clk added on i.mx7ulp.

- clocks : A list of phandle and clock-specifier pairs, one for each entry in

	clock-names.



Optional properties:

- big-endian: If present registers and hardware scatter/gather descriptors

	of the eDMA are implemented in big endian mode, otherwise in little

	mode.

- interrupt-names : Should contain the below on vf610 similar SoC but not used

	on i.mx7ulp similar SoC:

	"edma-tx" - the transmission interrupt

	"edma-err" - the error interrupt





Examples:



edma0: dma-controller@40018000 {

	#dma-cells = <2>;

	compatible = "fsl,vf610-edma";

	reg = <0x40018000 0x2000>,

		<0x40024000 0x1000>,

		<0x40025000 0x1000>;

	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,

		<0 9 IRQ_TYPE_LEVEL_HIGH>;

	interrupt-names = "edma-tx", "edma-err";

	dma-channels = <32>;

	clock-names = "dmamux0", "dmamux1";

	clocks = <&clks VF610_CLK_DMAMUX0>,

		<&clks VF610_CLK_DMAMUX1>;

}; /* vf610 */



edma1: dma-controller@40080000 {

	#dma-cells = <2>;

	compatible = "fsl,imx7ulp-edma";

	reg = <0x40080000 0x2000>,

		<0x40210000 0x1000>;

	dma-channels = <32>;

	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,

		     /* last is eDMA2-ERR interrupt */

		     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

	clock-names = "dma", "dmamux0";

	clocks = <&pcc2 IMX7ULP_CLK_DMA1>,

		 <&pcc2 IMX7ULP_CLK_DMA_MUX1>;

}; /* i.mx7ulp */



* DMA clients

DMA client drivers that uses the DMA function must use the format described

in the dma.txt file, using a two-cell specifier for each channel: the 1st

specifies the channel group(DMAMUX) in which this request can be multiplexed,

and the 2nd specifies the request source.



Examples:



sai2: sai@40031000 {

	compatible = "fsl,vf610-sai";

	reg = <0x40031000 0x1000>;

	interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;

	clock-names = "sai";

	clocks = <&clks VF610_CLK_SAI2>;

	dma-names = "tx", "rx";

	dmas = <&edma0 0 21>,

		<&edma0 0 20>;

};

Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml

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@@ -22,6 +22,7 @@ properties: 
      - items:

          - enum:

              - mediatek,mt2712-uart-dma

              - mediatek,mt8365-uart-dma

              - mediatek,mt8516-uart-dma

          - const: mediatek,mt6577-uart-dma

      - enum:

Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml

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@@ -23,7 +23,9 @@ properties: 
    oneOf:

      - const: nvidia,tegra186-gpcdma

      - items:

          - const: nvidia,tegra194-gpcdma

          - enum:

              - nvidia,tegra234-gpcdma

              - nvidia,tegra194-gpcdma

          - const: nvidia,tegra186-gpcdma



  "#dma-cells":