Merge branch 'for-next/sysreg' into for-next/core (eeb3557c) · Commits · EulixOS / Software / Kernel

arch/arm64/include/asm/sysreg.h

+0 −9

Original line number	Original line	Diff line number	Diff line
	@@ -419,9 +419,6 @@
	#define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)		#define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
	#define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)		#define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
	#define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)		#define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
	#define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4)
	#define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5)
	#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
	#define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)		#define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)

	#define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)		#define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
	@@ -758,12 +755,6 @@
	#define ICH_VTR_TDS_SHIFT 19		#define ICH_VTR_TDS_SHIFT 19
	#define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT)		#define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT)

	/* HFG[WR]TR_EL2 bit definitions */
	#define HFGxTR_EL2_nTPIDR2_EL0_SHIFT 55
	#define HFGxTR_EL2_nTPIDR2_EL0_MASK BIT_MASK(HFGxTR_EL2_nTPIDR2_EL0_SHIFT)
	#define HFGxTR_EL2_nSMPRI_EL1_SHIFT 54
	#define HFGxTR_EL2_nSMPRI_EL1_MASK BIT_MASK(HFGxTR_EL2_nSMPRI_EL1_SHIFT)

	#define ARM64_FEATURE_FIELD_BITS 4		#define ARM64_FEATURE_FIELD_BITS 4

	/* Defined for compatibility only, do not add new users. */		/* Defined for compatibility only, do not add new users. */

arch/arm64/kernel/idreg-override.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -167,7 +167,7 @@ static const struct {
	} aliases[] __initconst = {		} aliases[] __initconst = {
	{ "kvm-arm.mode=nvhe", "id_aa64mmfr1.vh=0" },		{ "kvm-arm.mode=nvhe", "id_aa64mmfr1.vh=0" },
	{ "kvm-arm.mode=protected", "id_aa64mmfr1.vh=0" },		{ "kvm-arm.mode=protected", "id_aa64mmfr1.vh=0" },
	{ "arm64.nosve", "id_aa64pfr0.sve=0 id_aa64pfr1.sme=0" },		{ "arm64.nosve", "id_aa64pfr0.sve=0" },
	{ "arm64.nosme", "id_aa64pfr1.sme=0" },		{ "arm64.nosme", "id_aa64pfr1.sme=0" },
	{ "arm64.nobti", "id_aa64pfr1.bt=0" },		{ "arm64.nobti", "id_aa64pfr1.bt=0" },
	{ "arm64.nopauth",		{ "arm64.nopauth",

arch/arm64/tools/gen-sysreg.awk

+58 −37

Original line number	Original line	Diff line number	Diff line
	@@ -4,23 +4,35 @@
	#		#
	# Usage: awk -f gen-sysreg.awk sysregs.txt		# Usage: awk -f gen-sysreg.awk sysregs.txt

			function block_current() {
			return __current_block[__current_block_depth];
			}

	# Log an error and terminate		# Log an error and terminate
	function fatal(msg) {		function fatal(msg) {
	print "Error at " NR ": " msg > "/dev/stderr"		print "Error at " NR ": " msg > "/dev/stderr"

			printf "Current block nesting:"

			for (i = 0; i <= __current_block_depth; i++) {
			printf " " __current_block[i]
			}
			printf "\n"

	exit 1		exit 1
	}		}

	# Sanity check that the start or end of a block makes sense at this point in		# Enter a new block, setting the active block to @block
	# the file. If not, produce an error and terminate.		function block_push(block) {
	#		__current_block[++__current_block_depth] = block
	# @this - the $Block or $EndBlock		}
	# @prev - the only valid block to already be in (value of @block)
	# @new - the new value of @block		# Exit a block, setting the active block to the parent block
	function change_block(this, prev, new) {		function block_pop() {
	if (block != prev)		if (__current_block_depth == 0)
	fatal("unexpected " this " (inside " block ")")		fatal("error: block_pop() in root block")

	block = new		__current_block_depth--;
	}		}

	# Sanity check the number of records for a field makes sense. If not, produce		# Sanity check the number of records for a field makes sense. If not, produce
	@@ -84,10 +96,14 @@ BEGIN {
	print "/* Generated file - do not edit */"		print "/* Generated file - do not edit */"
	print ""		print ""

	block = "None"		__current_block_depth = 0
			__current_block[__current_block_depth] = "Root"
	}		}

	END {		END {
			if (__current_block_depth != 0)
			fatal("Missing terminator for " block_current() " block")

	print "#endif /* __ASM_SYSREG_DEFS_H */"		print "#endif /* __ASM_SYSREG_DEFS_H */"
	}		}

	@@ -95,8 +111,9 @@ END {
	/^$/ { next }		/^$/ { next }
	/^[\t ]*#/ { next }		/^[\t ]*#/ { next }

	/^SysregFields/ {		/^SysregFields/ && block_current() == "Root" {
	change_block("SysregFields", "None", "SysregFields")		block_push("SysregFields")

	expect_fields(2)		expect_fields(2)

	reg = $2		reg = $2
	@@ -110,12 +127,10 @@ END {
	next		next
	}		}

	/^EndSysregFields/ {		/^EndSysregFields/ && block_current() == "SysregFields" {
	if (next_bit > 0)		if (next_bit > 0)
	fatal("Unspecified bits in " reg)		fatal("Unspecified bits in " reg)

	change_block("EndSysregFields", "SysregFields", "None")

	define(reg "_RES0", "(" res0 ")")		define(reg "_RES0", "(" res0 ")")
	define(reg "_RES1", "(" res1 ")")		define(reg "_RES1", "(" res1 ")")
	define(reg "_UNKN", "(" unkn ")")		define(reg "_UNKN", "(" unkn ")")
	@@ -126,11 +141,13 @@ END {
	res1 = null		res1 = null
	unkn = null		unkn = null

			block_pop()
	next		next
	}		}

	/^Sysreg/ {		/^Sysreg/ && block_current() == "Root" {
	change_block("Sysreg", "None", "Sysreg")		block_push("Sysreg")

	expect_fields(7)		expect_fields(7)

	reg = $2		reg = $2
	@@ -160,12 +177,10 @@ END {
	next		next
	}		}

	/^EndSysreg/ {		/^EndSysreg/ && block_current() == "Sysreg" {
	if (next_bit > 0)		if (next_bit > 0)
	fatal("Unspecified bits in " reg)		fatal("Unspecified bits in " reg)

	change_block("EndSysreg", "Sysreg", "None")

	if (res0 != null)		if (res0 != null)
	define(reg "_RES0", "(" res0 ")")		define(reg "_RES0", "(" res0 ")")
	if (res1 != null)		if (res1 != null)
	@@ -185,12 +200,13 @@ END {
	res1 = null		res1 = null
	unkn = null		unkn = null

			block_pop()
	next		next
	}		}

	# Currently this is effectivey a comment, in future we may want to emit		# Currently this is effectivey a comment, in future we may want to emit
	# defines for the fields.		# defines for the fields.
	/^Fields/ && (block == "Sysreg") {		/^Fields/ && block_current() == "Sysreg" {
	expect_fields(2)		expect_fields(2)

	if (next_bit != 63)		if (next_bit != 63)
	@@ -208,7 +224,7 @@ END {
	}		}


	/^Res0/ && (block == "Sysreg" \|\| block == "SysregFields") {		/^Res0/ && (block_current() == "Sysreg" \|\| block_current() == "SysregFields") {
	expect_fields(2)		expect_fields(2)
	parse_bitdef(reg, "RES0", $2)		parse_bitdef(reg, "RES0", $2)
	field = "RES0_" msb "_" lsb		field = "RES0_" msb "_" lsb
	@@ -218,7 +234,7 @@ END {
	next		next
	}		}

	/^Res1/ && (block == "Sysreg" \|\| block == "SysregFields") {		/^Res1/ && (block_current() == "Sysreg" \|\| block_current() == "SysregFields") {
	expect_fields(2)		expect_fields(2)
	parse_bitdef(reg, "RES1", $2)		parse_bitdef(reg, "RES1", $2)
	field = "RES1_" msb "_" lsb		field = "RES1_" msb "_" lsb
	@@ -228,7 +244,7 @@ END {
	next		next
	}		}

	/^Unkn/ && (block == "Sysreg" \|\| block == "SysregFields") {		/^Unkn/ && (block_current() == "Sysreg" \|\| block_current() == "SysregFields") {
	expect_fields(2)		expect_fields(2)
	parse_bitdef(reg, "UNKN", $2)		parse_bitdef(reg, "UNKN", $2)
	field = "UNKN_" msb "_" lsb		field = "UNKN_" msb "_" lsb
	@@ -238,7 +254,7 @@ END {
	next		next
	}		}

	/^Field/ && (block == "Sysreg" \|\| block == "SysregFields") {		/^Field/ && (block_current() == "Sysreg" \|\| block_current() == "SysregFields") {
	expect_fields(3)		expect_fields(3)
	field = $3		field = $3
	parse_bitdef(reg, field, $2)		parse_bitdef(reg, field, $2)
	@@ -249,15 +265,16 @@ END {
	next		next
	}		}

	/^Raz/ && (block == "Sysreg" \|\| block == "SysregFields") {		/^Raz/ && (block_current() == "Sysreg" \|\| block_current() == "SysregFields") {
	expect_fields(2)		expect_fields(2)
	parse_bitdef(reg, field, $2)		parse_bitdef(reg, field, $2)

	next		next
	}		}

	/^SignedEnum/ {		/^SignedEnum/ && (block_current() == "Sysreg" \|\| block_current() == "SysregFields") {
	change_block("Enum<", "Sysreg", "Enum")		block_push("Enum")

	expect_fields(3)		expect_fields(3)
	field = $3		field = $3
	parse_bitdef(reg, field, $2)		parse_bitdef(reg, field, $2)
	@@ -268,8 +285,9 @@ END {
	next		next
	}		}

	/^UnsignedEnum/ {		/^UnsignedEnum/ && (block_current() == "Sysreg" \|\| block_current() == "SysregFields") {
	change_block("Enum<", "Sysreg", "Enum")		block_push("Enum")

	expect_fields(3)		expect_fields(3)
	field = $3		field = $3
	parse_bitdef(reg, field, $2)		parse_bitdef(reg, field, $2)
	@@ -280,8 +298,9 @@ END {
	next		next
	}		}

	/^Enum/ {		/^Enum/ && (block_current() == "Sysreg" \|\| block_current() == "SysregFields") {
	change_block("Enum", "Sysreg", "Enum")		block_push("Enum")

	expect_fields(3)		expect_fields(3)
	field = $3		field = $3
	parse_bitdef(reg, field, $2)		parse_bitdef(reg, field, $2)
	@@ -291,16 +310,18 @@ END {
	next		next
	}		}

	/^EndEnum/ {		/^EndEnum/ && block_current() == "Enum" {
	change_block("EndEnum", "Enum", "Sysreg")
	field = null		field = null
	msb = null		msb = null
	lsb = null		lsb = null
	print ""		print ""

			block_pop()
	next		next
	}		}

	/0b[01]+/ && block == "Enum" {		/0b[01]+/ && block_current() == "Enum" {
	expect_fields(2)		expect_fields(2)
	val = $1		val = $1
	name = $2		name = $2

arch/arm64/tools/sysreg

+164 −1

Original line number	Original line	Diff line number	Diff line
	@@ -879,7 +879,30 @@ EndEnum
	EndSysreg		EndSysreg

	Sysreg ID_AA64PFR1_EL1 3 0 0 4 1		Sysreg ID_AA64PFR1_EL1 3 0 0 4 1
	Res0 63:40		UnsignedEnum 63:60 PFAR
			0b0000 NI
			0b0001 IMP
			EndEnum
			UnsignedEnum 59:56 DF2
			0b0000 NI
			0b0001 IMP
			EndEnum
			UnsignedEnum 55:52 MTEX
			0b0000 MTE
			0b0001 MTE4
			EndEnum
			UnsignedEnum 51:48 THE
			0b0000 NI
			0b0001 IMP
			EndEnum
			UnsignedEnum 47:44 GCS
			0b0000 NI
			0b0001 IMP
			EndEnum
			Enum 43:40 MTE_frac
			0b0000 ASYNC
			0b1111 NI
			EndEnum
	UnsignedEnum 39:36 NMI		UnsignedEnum 39:36 NMI
	0b0000 NI		0b0000 NI
	0b0001 IMP		0b0001 IMP
	@@ -1866,6 +1889,146 @@ Field 1 ZA
	Field 0 SM		Field 0 SM
	EndSysreg		EndSysreg

			SysregFields HFGxTR_EL2
			Field 63 nAMIAIR2_EL1
			Field 62 nMAIR2_EL1
			Field 61 nS2POR_EL1
			Field 60 nPOR_EL1
			Field 59 nPOR_EL0
			Field 58 nPIR_EL1
			Field 57 nPIRE0_EL1
			Field 56 nRCWMASK_EL1
			Field 55 nTPIDR2_EL0
			Field 54 nSMPRI_EL1
			Field 53 nGCS_EL1
			Field 52 nGCS_EL0
			Res0 51
			Field 50 nACCDATA_EL1
			Field 49 ERXADDR_EL1
			Field 48 EXRPFGCDN_EL1
			Field 47 EXPFGCTL_EL1
			Field 46 EXPFGF_EL1
			Field 45 ERXMISCn_EL1
			Field 44 ERXSTATUS_EL1
			Field 43 ERXCTLR_EL1
			Field 42 ERXFR_EL1
			Field 41 ERRSELR_EL1
			Field 40 ERRIDR_EL1
			Field 39 ICC_IGRPENn_EL1
			Field 38 VBAR_EL1
			Field 37 TTBR1_EL1
			Field 36 TTBR0_EL1
			Field 35 TPIDR_EL0
			Field 34 TPIDRRO_EL0
			Field 33 TPIDR_EL1
			Field 32 TCR_EL1
			Field 31 SCTXNUM_EL0
			Field 30 SCTXNUM_EL1
			Field 29 SCTLR_EL1
			Field 28 REVIDR_EL1
			Field 27 PAR_EL1
			Field 26 MPIDR_EL1
			Field 25 MIDR_EL1
			Field 24 MAIR_EL1
			Field 23 LORSA_EL1
			Field 22 LORN_EL1
			Field 21 LORID_EL1
			Field 20 LOREA_EL1
			Field 19 LORC_EL1
			Field 18 ISR_EL1
			Field 17 FAR_EL1
			Field 16 ESR_EL1
			Field 15 DCZID_EL0
			Field 14 CTR_EL0
			Field 13 CSSELR_EL1
			Field 12 CPACR_EL1
			Field 11 CONTEXTIDR_EL1
			Field 10 CLIDR_EL1
			Field 9 CCSIDR_EL1
			Field 8 APIBKey
			Field 7 APIAKey
			Field 6 APGAKey
			Field 5 APDBKey
			Field 4 APDAKey
			Field 3 AMAIR_EL1
			Field 2 AIDR_EL1
			Field 1 AFSR1_EL1
			Field 0 AFSR0_EL1
			EndSysregFields

			Sysreg HFGRTR_EL2 3 4 1 1 4
			Fields HFGxTR_EL2
			EndSysreg

			Sysreg HFGWTR_EL2 3 4 1 1 5
			Fields HFGxTR_EL2
			EndSysreg

			Sysreg HFGITR_EL2 3 4 1 1 6
			Res0 63:61
			Field 60 COSPRCTX
			Field 59 nGCSEPP
			Field 58 nGCSSTR_EL1
			Field 57 nGCSPUSHM_EL1
			Field 56 nBRBIALL
			Field 55 nBRBINJ
			Field 54 DCCVAC
			Field 53 SVC_EL1
			Field 52 SVC_EL0
			Field 51 ERET
			Field 50 CPPRCTX
			Field 49 DVPRCTX
			Field 48 CFPRCTX
			Field 47 TLBIVAALE1
			Field 46 TLBIVALE1
			Field 45 TLBIVAAE1
			Field 44 TLBIASIDE1
			Field 43 TLBIVAE1
			Field 42 TLBIVMALLE1
			Field 41 TLBIRVAALE1
			Field 40 TLBIRVALE1
			Field 39 TLBIRVAAE1
			Field 38 TLBIRVAE1
			Field 37 TLBIRVAALE1IS
			Field 36 TLBIRVALE1IS
			Field 35 TLBIRVAAE1IS
			Field 34 TLBIRVAE1IS
			Field 33 TLBIVAALE1IS
			Field 32 TLBIVALE1IS
			Field 31 TLBIVAAE1IS
			Field 30 TLBIASIDE1IS
			Field 29 TLBIVAE1IS
			Field 28 TLBIVMALLE1IS
			Field 27 TLBIRVAALE1OS
			Field 26 TLBIRVALE1OS
			Field 25 TLBIRVAAE1OS
			Field 24 TLBIRVAE1OS
			Field 23 TLBIVAALE1OS
			Field 22 TLBIVALE1OS
			Field 21 TLBIVAAE1OS
			Field 20 TLBIASIDE1OS
			Field 19 TLBIVAE1OS
			Field 18 TLBIVMALLE1OS
			Field 17 ATS1E1WP
			Field 16 ATS1E1RP
			Field 15 ATS1E0W
			Field 14 ATS1E0R
			Field 13 ATS1E1W
			Field 12 ATS1E1R
			Field 11 DCZVA
			Field 10 DCCIVAC
			Field 9 DCCVADP
			Field 8 DCCVAP
			Field 7 DCCVAU
			Field 6 DCCISW
			Field 5 DCCSW
			Field 4 DCISW
			Field 3 DCIVAC
			Field 2 ICIVAU
			Field 1 ICIALLU
			Field 0 ICIALLUIS
			EndSysreg

	Sysreg ZCR_EL2 3 4 1 2 0		Sysreg ZCR_EL2 3 4 1 2 0
	Fields ZCR_ELx		Fields ZCR_ELx
	EndSysreg		EndSysreg