Commit bbd329fe authored by Mark Brown's avatar Mark Brown Committed by Will Deacon
Browse files

arm64/sysreg: Convert HFGITR_EL2 to automatic generation 



Automatically generate the Hypervisor Fine-Grained Instruction Trap
Register as per DDI0601 2023-03, currently we only have a definition for
the register name not any of the contents.  No functional change.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230306-arm64-fgt-reg-gen-v5-1-516a89cb50f6@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent b2ad9d4e

arch/arm64/include/asm/sysreg.h

+0 −1
Original line number Diff line number Diff line
@@ -419,7 +419,6 @@ 
#define SYS_MDCR_EL2			sys_reg(3, 4, 1, 1, 1)

#define SYS_CPTR_EL2			sys_reg(3, 4, 1, 1, 2)

#define SYS_HSTR_EL2			sys_reg(3, 4, 1, 1, 3)

#define SYS_HFGITR_EL2			sys_reg(3, 4, 1, 1, 6)

#define SYS_HACR_EL2			sys_reg(3, 4, 1, 1, 7)



#define SYS_TTBR0_EL2			sys_reg(3, 4, 2, 0, 0)

arch/arm64/tools/sysreg

+65 −0
Original line number Diff line number Diff line
@@ -1964,6 +1964,71 @@ Sysreg HFGWTR_EL2 3 4 1 1 5 
Fields	HFGxTR_EL2

EndSysreg



Sysreg HFGITR_EL2	3	4	1	1	6

Res0	63:61

Field	60	COSPRCTX

Field	59	nGCSEPP

Field	58	nGCSSTR_EL1

Field	57	nGCSPUSHM_EL1

Field	56	nBRBIALL

Field	55	nBRBINJ

Field	54	DCCVAC

Field	53	SVC_EL1

Field	52	SVC_EL0

Field	51	ERET

Field	50	CPPRCTX

Field	49	DVPRCTX

Field	48	CFPRCTX

Field	47	TLBIVAALE1

Field	46	TLBIVALE1

Field	45	TLBIVAAE1

Field	44	TLBIASIDE1

Field	43	TLBIVAE1

Field	42	TLBIVMALLE1

Field	41	TLBIRVAALE1

Field	40	TLBIRVALE1

Field	39	TLBIRVAAE1

Field	38	TLBIRVAE1

Field	37	TLBIRVAALE1IS

Field	36	TLBIRVALE1IS

Field	35	TLBIRVAAE1IS

Field	34	TLBIRVAE1IS

Field	33	TLBIVAALE1IS

Field	32	TLBIVALE1IS

Field	31	TLBIVAAE1IS

Field	30	TLBIASIDE1IS

Field	29	TLBIVAE1IS

Field	28	TLBIVMALLE1IS

Field	27	TLBIRVAALE1OS

Field	26	TLBIRVALE1OS

Field	25	TLBIRVAAE1OS

Field	24	TLBIRVAE1OS

Field	23	TLBIVAALE1OS

Field	22	TLBIVALE1OS

Field	21	TLBIVAAE1OS

Field	20	TLBIASIDE1OS

Field	19	TLBIVAE1OS

Field	18	TLBIVMALLE1OS

Field	17	ATS1E1WP

Field	16	ATS1E1RP

Field	15	ATS1E0W

Field	14	ATS1E0R

Field	13	ATS1E1W

Field	12	ATS1E1R

Field	11	DCZVA

Field	10	DCCIVAC

Field	9	DCCVADP

Field	8	DCCVAP

Field	7	DCCVAU

Field	6	DCCISW

Field	5	DCCSW

Field	4	DCISW

Field	3	DCIVAC

Field	2	ICIVAU

Field	1	ICIALLU

Field	0	ICIALLUIS

EndSysreg



Sysreg	ZCR_EL2	3	4	1	2	0

Fields	ZCR_ELx

EndSysreg