perf/x86/cstate: Add Alder Lake CPU support

mainline inclusion
from mainline-v5.13-rc1
commit d0ca946b
category: feature
feature: SRF core PMU support
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8RWG5
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d0ca946bcf84e1f9847571923bb1e6bd1264f424



Intel-SIG: commit d0ca946b perf/x86/cstate: Add Alder Lake CPU support
Backport as a dependency for Sierra Forrest core PMU support.

-------------------------------------

Compared with the Rocket Lake, the CORE C1 Residency Counter is added
for Alder Lake, but the CORE C3 Residency Counter is removed. Other
counters are the same.

Create a new adl_cstates for Alder Lake. Update the comments
accordingly.

The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.

The patch has been tested on real hardware.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/1618237865-33448-25-git-send-email-kan.liang@linux.intel.com


Signed-off-by: Yunying Sun <yunying.sun@intel.com>