Unverified Commit ed7595f1 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!10799 Intel: Backport 3 core PMU bugfixes to kernel 5.10 

Merge Pull Request from: @yunyingsun 
 
Content:
In mainline kernel before v6.11-rc1, PMU name for Intel next Xeon Granite Rapids(GNR) is the same as 4th and 5th gen Xeon(SPR and EMR). A new bugfix makes GNR using a different name for PMU.

The fix patch is among a patch set of three which just landed mainline kernel v6.11-rc1:
fa0c1c9d283b perf/x86/intel: Add a distinct name for Granite Rapids
e5f32ad56b22 perf/x86/intel/ds: Fix non 0 retire latency on Raptorlake
556a7c039a52 perf/x86/intel: Hide Topdown metrics events if the feature is not enumerated

This PR is to backport above fixes to kernel 5.10 for better GNR PMU support.

Intel-kernel issue:
https://gitee.com/openeuler/intel-kernel/issues/IAIG7E

Test:
Before backport on GNR, "dmesg | grep -i 'performance events'" shows "Sapphire Rapids events".
After backport on GNR, "dmesg | grep -i 'performance events'" shows "Granite Rapids events".

Known issue:
N/A

Configs:
N/A

Note: The backported patches were applied manually to kernel 5.10 with some adjustments, but no extra code changes comparing to upstream version. The backported patch set has been verified on Intel internal GNR. 
 
Link:https://gitee.com/openeuler/kernel/pulls/10799

 

Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Signed-off-by: default avatarYang Yingliang <yangyingliang@huawei.com>
parents 37fbb7ba 3fcf0fb6

arch/x86/events/intel/core.c

+41 −6
Original line number Diff line number Diff line
@@ -5525,8 +5525,22 @@ default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 
	return attr->mode;

}



static umode_t

td_is_visible(struct kobject *kobj, struct attribute *attr, int i)

{

	/*

	 * Hide the perf metrics topdown events

	 * if the feature is not enumerated.

	 */

	if (x86_pmu.num_topdown_events)

		return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0;



	return attr->mode;

}



static struct attribute_group group_events_td  = {

	.name = "events",

	.is_visible = td_is_visible,

};



static struct attribute_group group_events_mem = {
@@ -5728,9 +5742,26 @@ static umode_t hybrid_format_is_visible(struct kobject *kobj, 
	return (cpu >= 0) && (pmu->cpu_type & pmu_attr->pmu_type) ? attr->mode : 0;

}



static umode_t hybrid_td_is_visible(struct kobject *kobj,

				    struct attribute *attr, int i)

{

	struct device *dev = kobj_to_dev(kobj);

	struct x86_hybrid_pmu *pmu =

		 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);



	if (!is_attr_for_this_pmu(kobj, attr))

		return 0;



	/* Only the big core supports perf metrics */

	if (pmu->cpu_type == hybrid_big)

		return pmu->intel_cap.perf_metrics ? attr->mode : 0;



	return attr->mode;

}



static struct attribute_group hybrid_group_events_td  = {

	.name		= "events",

	.is_visible	= hybrid_events_is_visible,

	.is_visible	= hybrid_td_is_visible,

};



static struct attribute_group hybrid_group_events_mem = {
@@ -6542,9 +6573,17 @@ __init int intel_pmu_init(void) 
	case INTEL_FAM6_EMERALDRAPIDS_X:

		x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;

		x86_pmu.extra_regs = intel_spr_extra_regs;

		fallthrough;

		pr_cont("Sapphire Rapids events, ");

		name = "sapphire_rapids";

		goto glc_common;



	case INTEL_FAM6_GRANITERAPIDS_X:

	case INTEL_FAM6_GRANITERAPIDS_D:

		x86_pmu.extra_regs = intel_gnr_extra_regs;

		pr_cont("Granite Rapids events, ");

		name = "granite_rapids";



	glc_common:

		pmem = true;

		x86_pmu.late_ack = true;

		memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids));
@@ -6552,8 +6591,6 @@ __init int intel_pmu_init(void) 


		x86_pmu.event_constraints = intel_spr_event_constraints;

		x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;

		if (!x86_pmu.extra_regs)

			x86_pmu.extra_regs = intel_gnr_extra_regs;

		x86_pmu.limit_period = spr_limit_period;

		x86_pmu.pebs_aliases = NULL;

		x86_pmu.pebs_prec_dist = true;
@@ -6577,8 +6614,6 @@ __init int intel_pmu_init(void) 
		x86_pmu.num_topdown_events = 8;

		x86_pmu.update_topdown_event = icl_update_topdown_event;

		x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;

		pr_cont("Sapphire Rapids events, ");

		name = "sapphire_rapids";

		break;



	case INTEL_FAM6_ALDERLAKE:

arch/x86/events/intel/ds.c

+6 −2
Original line number Diff line number Diff line
@@ -1778,8 +1778,12 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event, 
	set_linear_ip(regs, basic->ip);

	regs->flags = PERF_EFLAGS_EXACT;



	if ((sample_type & PERF_SAMPLE_WEIGHT_STRUCT) && (x86_pmu.flags & PMU_FL_RETIRE_LATENCY))

	if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT) {

		if (x86_pmu.flags & PMU_FL_RETIRE_LATENCY)

			data->weight.var3_w = format_size >> PEBS_RETIRE_LATENCY_OFFSET & PEBS_LATENCY_MASK;

		else

			data->weight.var3_w = 0;

	}



	/*

	 * The record for MEMINFO is in front of GP