Commit 3fcf0fb6 authored by Kan Liang's avatar Kan Liang Committed by Yunying Sun
Browse files

perf/x86/intel: Add a distinct name for Granite Rapids 

mainline inclusion
from mainline-v6.11-rc1
commit fa0c1c9d283b37fdb7fc1dcccbb88fc8f48a4aa4
category: bugfix
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/IAIG7E
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=fa0c1c9d283b37fdb7fc1dcccbb88fc8f48a4aa4



-------------------------------------

Currently, the Sapphire Rapids and Granite Rapids share the same PMU
name, sapphire_rapids. Because from the kernel’s perspective, GNR is
similar to SPR. The only key difference is that they support different
extra MSRs. The code path and the PMU name are shared.

However, from end users' perspective, they are quite different. Besides
the extra MSRs, GNR has a newer PEBS format, supports Retire Latency,
supports new CPUID enumeration architecture, doesn't required the
load-latency AUX event, has additional TMA Level 1 Architectural Events,
etc. The differences can be enumerated by CPUID or the PERF_CAPABILITIES
MSR. They weren't reflected in the model-specific kernel setup.
But it is worth to have a distinct PMU name for GNR.

Intel-SIG: commit fa0c1c9d283b perf/x86/intel: Add a distinct name for Granite Rapids
Backport some core PMU bugfixes to kernel 5.10

Fixes: a6742cb9 ("perf/x86/intel: Fix the FRONTEND encoding on GNR and MTL")
Suggested-by: default avatarAhmad Yasin <ahmad.yasin@intel.com>
Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20240708193336.1192217-3-kan.liang@linux.intel.com


Signed-off-by: default avatarYunying Sun <yunying.sun@intel.com>
parent 8fd2c7e0

arch/x86/events/intel/core.c

+9 −5
Original line number Diff line number Diff line
@@ -6573,9 +6573,17 @@ __init int intel_pmu_init(void) 
	case INTEL_FAM6_EMERALDRAPIDS_X:

		x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;

		x86_pmu.extra_regs = intel_spr_extra_regs;

		fallthrough;

		pr_cont("Sapphire Rapids events, ");

		name = "sapphire_rapids";

		goto glc_common;



	case INTEL_FAM6_GRANITERAPIDS_X:

	case INTEL_FAM6_GRANITERAPIDS_D:

		x86_pmu.extra_regs = intel_gnr_extra_regs;

		pr_cont("Granite Rapids events, ");

		name = "granite_rapids";



	glc_common:

		pmem = true;

		x86_pmu.late_ack = true;

		memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids));
@@ -6583,8 +6591,6 @@ __init int intel_pmu_init(void) 


		x86_pmu.event_constraints = intel_spr_event_constraints;

		x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;

		if (!x86_pmu.extra_regs)

			x86_pmu.extra_regs = intel_gnr_extra_regs;

		x86_pmu.limit_period = spr_limit_period;

		x86_pmu.pebs_aliases = NULL;

		x86_pmu.pebs_prec_dist = true;
@@ -6608,8 +6614,6 @@ __init int intel_pmu_init(void) 
		x86_pmu.num_topdown_events = 8;

		x86_pmu.update_topdown_event = icl_update_topdown_event;

		x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;

		pr_cont("Sapphire Rapids events, ");

		name = "sapphire_rapids";

		break;



	case INTEL_FAM6_ALDERLAKE: