Commit ed447e7d authored by Kieran Bingham's avatar Kieran Bingham Committed by Geert Uytterhoeven
Browse files

clk: renesas: r8a779a0: Add VSPD clock support 



Add clocks for the VSPD modules on the V3U.

Signed-off-by: default avatarKieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20201216151931.851547-3-kieran.bingham+renesas@ideasonboard.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 0177b509

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+2 −0
Original line number Diff line number Diff line
@@ -190,6 +190,8 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 
	DEF_MOD("vin35",	827,	R8A779A0_CLK_S1D1),

	DEF_MOD("vin36",	828,	R8A779A0_CLK_S1D1),

	DEF_MOD("vin37",	829,	R8A779A0_CLK_S1D1),

	DEF_MOD("vspd0",	830,	R8A779A0_CLK_S3D1),

	DEF_MOD("vspd1",	831,	R8A779A0_CLK_S3D1),

};



static spinlock_t cpg_lock;