Commit 0177b509 authored by Kieran Bingham's avatar Kieran Bingham Committed by Geert Uytterhoeven
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clk: renesas: r8a779a0: Add FCPVD clock support 



Add clocks for the FCP for VSP-D module.

Signed-off-by: default avatarKieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20201216151931.851547-2-kieran.bingham+renesas@ideasonboard.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent fa7f4797

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+2 −0
Original line number Diff line number Diff line
@@ -152,6 +152,8 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 
	DEF_MOD("csi41",	400,	R8A779A0_CLK_CSI0),

	DEF_MOD("csi42",	401,	R8A779A0_CLK_CSI0),

	DEF_MOD("csi43",	402,	R8A779A0_CLK_CSI0),

	DEF_MOD("fcpvd0",	508,	R8A779A0_CLK_S3D1),

	DEF_MOD("fcpvd1",	509,	R8A779A0_CLK_S3D1),

	DEF_MOD("scif0",	702,	R8A779A0_CLK_S1D8),

	DEF_MOD("scif1",	703,	R8A779A0_CLK_S1D8),

	DEF_MOD("scif3",	704,	R8A779A0_CLK_S1D8),