Commit ecf8eca5 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/xehp: Add compute engine ABI 

We're now ready to start exposing compute engines to userspace.

v2:
 - Move kerneldoc for other engine classes to a separate patch.  (Andi)

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Szymon Morek <szymon.morek@intel.com>
UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Acked-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: default avatarJordan Justen <jordan.l.justen@intel.com>
Tested-by: Jordan Justen <jordan.l.justen@intel.com>  # mesa anvil & iris
Link: https://patchwork.freedesktop.org/patch/msgid/20220428041926.1483683-4-matthew.d.roper@intel.com
parent 97e17a09

drivers/gpu/drm/i915/gt/intel_engine_user.c

+1 −1
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ static const u8 uabi_classes[] = { 
	[COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,

	[VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,

	[VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,

	/* TODO: Add COMPUTE_CLASS mapping once ABI is available */

	[COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,

};



static int engine_cmp(void *priv, const struct list_head *A,

drivers/gpu/drm/i915/i915_drm_client.c

+1 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = { 
	[I915_ENGINE_CLASS_COPY] = "copy",

	[I915_ENGINE_CLASS_VIDEO] = "video",

	[I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",

	[I915_ENGINE_CLASS_COMPUTE] = "compute",

};



static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)

drivers/gpu/drm/i915/i915_drm_client.h

+1 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 


#include "gt/intel_engine_types.h"



#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE

#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE



struct drm_i915_private;

include/uapi/drm/i915_drm.h

+9 −0
Original line number Diff line number Diff line
@@ -203,6 +203,15 @@ enum drm_i915_gem_engine_class { 
	 */

	I915_ENGINE_CLASS_VIDEO_ENHANCE	= 3,



	/**

	 * @I915_ENGINE_CLASS_COMPUTE:

	 *

	 * Compute engines support a subset of the instructions available

	 * on render engines:  compute engines support Compute (GPGPU) and

	 * programmable media workloads, but do not support the 3D pipeline.

	 */

	I915_ENGINE_CLASS_COMPUTE	= 4,



	/* Values in this enum should be kept compact. */



	/**