Commit 97e17a09 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/xehp: Add register for compute engine's MMIO-based TLB invalidation 



Compute engines have a separate register that the driver should use to
perform MMIO-based TLB invalidation.

Note that the term "context" in this register's bspec description is
used to refer to the engine instance (in the same way "context" is used
on bspec 46167).

Bspec: 43930
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Acked-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarPrathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220428041926.1483683-3-matthew.d.roper@intel.com
parent 991b4de3

drivers/gpu/drm/i915/gt/intel_gt.c

+1 −0
Original line number Diff line number Diff line
@@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) 
		[VIDEO_DECODE_CLASS]		= GEN12_VD_TLB_INV_CR,

		[VIDEO_ENHANCEMENT_CLASS]	= GEN12_VE_TLB_INV_CR,

		[COPY_ENGINE_CLASS]		= GEN12_BLT_TLB_INV_CR,

		[COMPUTE_CLASS]			= GEN12_COMPCTX_TLB_INV_CR,

	};

	struct drm_i915_private *i915 = gt->i915;

	struct intel_uncore *uncore = gt->uncore;

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -1007,6 +1007,7 @@ 
#define GEN12_VD_TLB_INV_CR			_MMIO(0xcedc)

#define GEN12_VE_TLB_INV_CR			_MMIO(0xcee0)

#define GEN12_BLT_TLB_INV_CR			_MMIO(0xcee4)

#define GEN12_COMPCTX_TLB_INV_CR		_MMIO(0xcf04)



#define GEN12_MERT_MOD_CTRL			_MMIO(0xcf28)

#define RENDER_MOD_CTRL				_MMIO(0xcf2c)