Commit ec4b70db authored by Taimur Hassan's avatar Taimur Hassan Committed by Alex Deucher
Browse files

drm/amd/display: Fix typo in enable and disable symclk_se 



[Why & How]
Symclk should be based on link_enc_inst, and symclk_fe_sel should be based
on stream_enc_inst.

Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarTaimur Hassan <syed.hassan@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 927e784c

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+3 −1
Original line number Diff line number Diff line
@@ -1150,6 +1150,7 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 
	struct timing_generator *tg = pipe_ctx->stream_res.tg;

	struct dtbclk_dto_params dto_params = {0};

	int dp_hpo_inst;

	struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);

	struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;



	if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
@@ -1178,7 +1179,8 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 
		dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

		dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);

	} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && dccg->funcs->disable_symclk_se)

		dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst);

		dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,

				link_enc->transmitter - TRANSMITTER_UNIPHY_A);



	if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

		/* TODO: This looks like a bug to me as we are disabling HPO IO when

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

+2 −1
Original line number Diff line number Diff line
@@ -180,7 +180,8 @@ struct dccg_funcs { 


	void (*disable_symclk_se)(

			struct dccg *dccg,

			uint32_t stream_enc_inst);

			uint32_t stream_enc_inst,

			uint32_t link_enc_inst);

};



#endif //__DAL_DCCG_H__