Commit 927e784c authored by Taimur Hassan's avatar Taimur Hassan Committed by Alex Deucher
Browse files

drm/amd/display: Add symclk enable/disable during stream enable/disable 



[Why & How]
Using dig_stream_mapper, program symclk_en and symclk_fe_src_sel when
enabling or disabling the corresponding stream.

Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarTaimur Hassan <syed.hassan@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4c340d00

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+3 −1
Original line number Diff line number Diff line
@@ -1150,6 +1150,7 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 
	struct timing_generator *tg = pipe_ctx->stream_res.tg;

	struct dtbclk_dto_params dto_params = {0};

	int dp_hpo_inst;

	struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;



	if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {

		pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
@@ -1176,7 +1177,8 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 
		dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

		dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

		dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);

	}

	} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && dccg->funcs->disable_symclk_se)

		dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst);



	if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

		/* TODO: This looks like a bug to me as we are disabling HPO IO when

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+5 −1
Original line number Diff line number Diff line
@@ -2719,6 +2719,8 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 
	struct dce_hwseq *hws = dc->hwseq;

	unsigned int k1_div = PIXEL_RATE_DIV_NA;

	unsigned int k2_div = PIXEL_RATE_DIV_NA;

	struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);

	struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;



	if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

		if (dc->hwseq->funcs.setup_hpo_hw_control)
@@ -2738,7 +2740,9 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 
		dto_params.timing = &pipe_ctx->stream->timing;

		dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);

		dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

	}

	} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && dccg->funcs->enable_symclk_se)

		dccg->funcs->enable_symclk_se(dccg,

			stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A);



	if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {

		hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

+9 −0
Original line number Diff line number Diff line
@@ -172,6 +172,15 @@ struct dccg_funcs { 
			struct dccg *dccg,

			unsigned int dpp_inst,

			bool clock_on);



	void (*enable_symclk_se)(

			struct dccg *dccg,

			uint32_t stream_enc_inst,

			uint32_t link_enc_inst);



	void (*disable_symclk_se)(

			struct dccg *dccg,

			uint32_t stream_enc_inst);

};



#endif //__DAL_DCCG_H__

drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h

+1 −0
Original line number Diff line number Diff line
@@ -269,6 +269,7 @@ struct stream_encoder_funcs { 
		struct stream_encoder *enc, unsigned int pix_per_container);

	void (*enable_fifo)(struct stream_encoder *enc);

	void (*disable_fifo)(struct stream_encoder *enc);

	void (*map_stream_to_link)(struct stream_encoder *enc, uint32_t stream_enc_inst, uint32_t link_enc_inst);

};



struct hpo_dp_stream_encoder_state {

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

+3 −0
Original line number Diff line number Diff line
@@ -46,6 +46,9 @@ void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx) 
	if (dc_is_dp_signal(pipe_ctx->stream->signal))

		pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(pipe_ctx->stream->link,

				DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_BE);

	if (stream_enc->funcs->map_stream_to_link)

		stream_enc->funcs->map_stream_to_link(stream_enc,

				stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A);

	if (stream_enc->funcs->enable_fifo)

		stream_enc->funcs->enable_fifo(stream_enc);

}