Commit eb651280 authored by Bang Li's avatar Bang Li Committed by Liu Shixin
Browse files

mm: implement update_mmu_tlb() using update_mmu_tlb_range() 

mainline inclusion
from mainline-v6.11-rc1
commit 8f65aa32239f1c3f11b7a25bd5921223bafc5fed
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IAIHPC

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8f65aa32239f1c3f11b7a25bd5921223bafc5fed

--------------------------------

Let's make update_mmu_tlb() simply a generic wrapper around
update_mmu_tlb_range().  Only the latter can now be overridden by the
architecture.  We can now remove __HAVE_ARCH_UPDATE_MMU_TLB as well.

Link: https://lkml.kernel.org/r/20240522061204.117421-3-libang.li@antgroup.com


Signed-off-by: default avatarBang Li <libang.li@antgroup.com>
Acked-by: default avatarDavid Hildenbrand <david@redhat.com>
Cc: Chris Zankel <chris@zankel.net>
Cc: Huacai Chen <chenhuacai@kernel.org>
Cc: Lance Yang <ioworker0@gmail.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Ryan Roberts <ryan.roberts@arm.com>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLiu Shixin <liushixin2@huawei.com>
parent 1eb4dfac

arch/loongarch/include/asm/pgtable.h

+0 −2
Original line number Diff line number Diff line
@@ -470,8 +470,6 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf, 
#define update_mmu_cache(vma, addr, ptep) \

	update_mmu_cache_range(NULL, vma, addr, ptep, 1)



#define __HAVE_ARCH_UPDATE_MMU_TLB

#define update_mmu_tlb	update_mmu_cache

#define update_mmu_tlb_range(vma, addr, ptep, nr) \

	update_mmu_cache_range(NULL, vma, addr, ptep, nr)

arch/mips/include/asm/pgtable.h

+0 −2
Original line number Diff line number Diff line
@@ -594,8 +594,6 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf, 
#define update_mmu_cache(vma, address, ptep) \

	update_mmu_cache_range(NULL, vma, address, ptep, 1)



#define	__HAVE_ARCH_UPDATE_MMU_TLB

#define update_mmu_tlb	update_mmu_cache

#define update_mmu_tlb_range(vma, address, ptep, nr) \

	update_mmu_cache_range(NULL, vma, address, ptep, nr)

arch/riscv/include/asm/pgtable.h

+0 −2
Original line number Diff line number Diff line
@@ -491,8 +491,6 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf, 
#define update_mmu_cache(vma, addr, ptep) \

	update_mmu_cache_range(NULL, vma, addr, ptep, 1)



#define __HAVE_ARCH_UPDATE_MMU_TLB

#define update_mmu_tlb update_mmu_cache

#define update_mmu_tlb_range(vma, addr, ptep, nr) \

	update_mmu_cache_range(NULL, vma, addr, ptep, nr)

arch/xtensa/include/asm/pgtable.h

+0 −3
Original line number Diff line number Diff line
@@ -410,9 +410,6 @@ void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma, 


typedef pte_t *pte_addr_t;



void update_mmu_tlb(struct vm_area_struct *vma,

		    unsigned long address, pte_t *ptep);

#define __HAVE_ARCH_UPDATE_MMU_TLB

void update_mmu_tlb_range(struct vm_area_struct *vma,

		unsigned long address, pte_t *ptep, unsigned int nr);

#define update_mmu_tlb_range update_mmu_tlb_range

arch/xtensa/mm/tlb.c

+0 −6
Original line number Diff line number Diff line
@@ -163,12 +163,6 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) 
	}

}



void update_mmu_tlb(struct vm_area_struct *vma,

		    unsigned long address, pte_t *ptep)

{

	local_flush_tlb_page(vma, address);

}



void update_mmu_tlb_range(struct vm_area_struct *vma,

			unsigned long address, pte_t *ptep, unsigned int nr)

{