Commit eb5b2011 authored by Lu Baolu's avatar Lu Baolu Committed by Joerg Roedel
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iommu/vt-d: Avoid unnecessary global IRTE cache invalidation



Some VT-d hardware implementations invalidate all interrupt remapping
hardware translation caches as part of SIRTP flow. The VT-d spec adds
a ESIRTPS (Enhanced Set Interrupt Remap Table Pointer Support, section
11.4.2 in VT-d spec) capability bit to indicate this.

The spec also states in 11.4.4 that hardware also performs global
invalidation on all interrupt remapping caches as part of Interrupt
Remapping Disable operation if ESIRTPS capability bit is set.

This checks the ESIRTPS capability bit and skip software global cache
invalidation if it's set.

Signed-off-by: default avatarJacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: default avatarJerry Snitselaar <jsnitsel@redhat.com>
Reviewed-by: default avatarKevin Tian <kevin.tian@intel.com>
Link: https://lore.kernel.org/r/20220921065741.3572495-1-baolu.lu@linux.intel.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent b722cb32
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+1 −0
Original line number Diff line number Diff line
@@ -146,6 +146,7 @@
/*
 * Decoding Capability Register
 */
#define cap_esirtps(c)		(((c) >> 62) & 1)
#define cap_fl5lp_support(c)	(((c) >> 60) & 1)
#define cap_pi_support(c)	(((c) >> 59) & 1)
#define cap_fl1gp_support(c)	(((c) >> 56) & 1)
+4 −2
Original line number Diff line number Diff line
@@ -494,6 +494,7 @@ static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
	 * Global invalidation of interrupt entry cache to make sure the
	 * hardware uses the new irq remapping table.
	 */
	if (!cap_esirtps(iommu->cap))
		qi_global_iec(iommu);
}

@@ -680,6 +681,7 @@ static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
	 * global invalidation of interrupt entry cache before disabling
	 * interrupt-remapping.
	 */
	if (!cap_esirtps(iommu->cap))
		qi_global_iec(iommu);

	raw_spin_lock_irqsave(&iommu->register_lock, flags);