Commit e95afc1c authored by Sung Joon Kim's avatar Sung Joon Kim Committed by Alex Deucher
Browse files

drm/amd/display: Enable AdaptiveSync in DC interface 



[why]
Start enabling AdaptiveSync feature on Linux environment.

[how]
Adding AdaptiveSync support in DC layer
- building AdaptiveSync info_packets
- adjusting the v_startup parameter

Reviewed-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Acked-by: default avatarAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: default avatarSung Joon Kim <sungjoon.kim@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 235fef6c

drivers/gpu/drm/amd/display/dc/core/dc.c

+4 −0
Original line number Diff line number Diff line
@@ -2960,6 +2960,9 @@ static void copy_stream_update_to_stream(struct dc *dc, 
	if (update->vsp_infopacket)

		stream->vsp_infopacket = *update->vsp_infopacket;



	if (update->adaptive_sync_infopacket)

		stream->adaptive_sync_infopacket = *update->adaptive_sync_infopacket;



	if (update->dither_option)

		stream->dither_option = *update->dither_option;
@@ -3165,6 +3168,7 @@ static void commit_planes_do_stream_update(struct dc *dc, 
					stream_update->vsc_infopacket ||

					stream_update->vsp_infopacket ||

					stream_update->hfvsif_infopacket ||

					stream_update->adaptive_sync_infopacket ||

					stream_update->vtem_infopacket) {

				resource_build_info_frame(pipe_ctx);

				dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+49 −0
Original line number Diff line number Diff line
@@ -3270,6 +3270,50 @@ static void set_hfvs_info_packet( 
	*info_packet = stream->hfvsif_infopacket;

}



static void adaptive_sync_override_dp_info_packets_sdp_line_num(

		const struct dc_crtc_timing *timing,

		struct enc_sdp_line_num *sdp_line_num,

		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param)

{

	uint32_t asic_blank_start = 0;

	uint32_t asic_blank_end   = 0;

	uint32_t v_update = 0;



	const struct dc_crtc_timing *tg = timing;



	/* blank_start = frame end - front porch */

	asic_blank_start = tg->v_total - tg->v_front_porch;



	/* blank_end = blank_start - active */

	asic_blank_end = (asic_blank_start - tg->v_border_bottom -

						tg->v_addressable - tg->v_border_top);



	if (pipe_dlg_param->vstartup_start > asic_blank_end) {

		v_update = (tg->v_total - (pipe_dlg_param->vstartup_start - asic_blank_end));

		sdp_line_num->adaptive_sync_line_num_valid = true;

		sdp_line_num->adaptive_sync_line_num = (tg->v_total - v_update - 1);

	} else {

		sdp_line_num->adaptive_sync_line_num_valid = false;

		sdp_line_num->adaptive_sync_line_num = 0;

	}

}



static void set_adaptive_sync_info_packet(

		struct dc_info_packet *info_packet,

		const struct dc_stream_state *stream,

		struct encoder_info_frame *info_frame,

		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param)

{

	if (!stream->adaptive_sync_infopacket.valid)

		return;



	adaptive_sync_override_dp_info_packets_sdp_line_num(

			&stream->timing,

			&info_frame->sdp_line_num,

			pipe_dlg_param);



	*info_packet = stream->adaptive_sync_infopacket;

}



static void set_vtem_info_packet(

		struct dc_info_packet *info_packet,
@@ -3362,6 +3406,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) 
	info->vsc.valid = false;

	info->hfvsif.valid = false;

	info->vtem.valid = false;

	info->adaptive_sync.valid = false;

	signal = pipe_ctx->stream->signal;



	/* HDMi and DP have different info packets*/
@@ -3382,6 +3427,10 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) 
		set_spd_info_packet(&info->spd, pipe_ctx->stream);



		set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);

		set_adaptive_sync_info_packet(&info->adaptive_sync,

										pipe_ctx->stream,

										info,

										&pipe_ctx->pipe_dlg_param);

	}



	patch_gamut_packet_checksum(&info->gamut);

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -1414,6 +1414,7 @@ struct dpcd_caps { 
	union dpcd_fec_capability fec_cap;

	struct dpcd_dsc_capabilities dsc_caps;

	struct dc_lttpr_caps lttpr_caps;

	struct adaptive_sync_caps adaptive_sync_caps;

	struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info;



	union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

+20 −1
Original line number Diff line number Diff line
@@ -502,7 +502,11 @@ union down_spread_ctrl { 
	1 = Main link signal is downspread <= 0.5%

	with frequency in the range of 30kHz ~ 33kHz*/

		uint8_t SPREAD_AMP:1;

		uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/

		uint8_t RESERVED2:1;/*Bit 5 = RESERVED. Read all 0s*/

	/* Bit 6 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE.

	0 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is not enabled by the Source device (default)

	1 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is enabled by Source device */

		uint8_t FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE:1;

	/*Bit 7 = MSA_TIMING_PAR_IGNORE_EN

	0 = Source device will send valid data for the MSA Timing Params

	1 = Source device may send invalid data for these MSA Timing Params*/
@@ -858,6 +862,21 @@ struct psr_caps { 
	unsigned int psr_power_opt_flag;

};



union dpcd_dprx_feature_enumeration_list_cont_1 {

	struct {

		uint8_t ADAPTIVE_SYNC_SDP_SUPPORT:1;

		uint8_t AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED: 1;

		uint8_t RESERVED0: 2;

		uint8_t VSC_EXT_SDP_VER1_SUPPORT: 1;

		uint8_t RESERVED1: 3;

	} bits;

	uint8_t raw;

};



struct adaptive_sync_caps {

	union dpcd_dprx_feature_enumeration_list_cont_1 dp_adap_sync_caps;

};



/* Length of router topology ID read from DPCD in bytes. */

#define DPCD_USB4_TOPOLOGY_ID_LEN 5

drivers/gpu/drm/amd/display/dc/dc_link.h

+1 −0
Original line number Diff line number Diff line
@@ -280,6 +280,7 @@ struct dc_link { 
		bool dp_keep_receiver_powered;

		bool dp_skip_DID2;

		bool dp_skip_reset_segment;

		bool dp_skip_fs_144hz;

		bool dp_mot_reset_segment;

		/* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */

		bool dpia_mst_dsc_always_on;