Commit 235fef6c authored by Samson Tam's avatar Samson Tam Committed by Alex Deucher
Browse files

drm/amd/display: adjust MALL size available for DCN32 and DCN321 



[Why]
MALL size available can vary for different SKUs.
Use num_chans read from VBIOS to determine the available MALL size we can use

[How]
Define max_chans for DCN32 and DCN321.
If num_chans is max_chans, then return max_chans as we can access the
 entire MALL space.
Otherwise, define avail_chans as the number of available channels we are
 allowed instead.
Return corresponding number of channels back and use this to calculate
 available MALL size.

Reviewed-by: default avatarNevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: default avatarAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: default avatarSamson Tam <Samson.Tam@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 01ecd870

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

+60 −2
Original line number Diff line number Diff line
@@ -2150,13 +2150,19 @@ static bool dcn32_resource_construct( 
	dc->caps.max_cursor_size = 64;

	dc->caps.min_horizontal_blanking_period = 80;

	dc->caps.dmdata_alloc_size = 2048;

	dc->caps.mall_size_per_mem_channel = 0;

	dc->caps.mall_size_per_mem_channel = 4;

	dc->caps.mall_size_total = 0;

	dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;



	dc->caps.cache_line_size = 64;

	dc->caps.cache_num_ways = 16;

	dc->caps.max_cab_allocation_bytes = 67108864; // 64MB = 1024 * 1024 * 64



	/* Calculate the available MALL space */

	dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(

		dc, dc->ctx->dc_bios->vram_info.num_chans) *

		dc->caps.mall_size_per_mem_channel * 1024 * 1024;

	dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;



	dc->caps.subvp_fw_processing_delay_us = 15;

	dc->caps.subvp_drr_max_vblank_margin_us = 40;

	dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
@@ -2593,3 +2599,55 @@ struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( 


	return idle_pipe;

}



unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans)

{

	/*

	 * DCN32 and DCN321 SKUs may have different sizes for MALL

	 *  but we may not be able to access all the MALL space.

	 *  If the num_chans is power of 2, then we can access all

	 *  of the available MALL space.  Otherwise, we can only

	 *  access:

	 *

	 *  max_cab_size_in_bytes = total_cache_size_in_bytes *

	 *    ((2^floor(log2(num_chans)))/num_chans)

	 *

	 * Calculating the MALL sizes for all available SKUs, we

	 *  have come up with the follow simplified check.

	 * - we have max_chans which provides the max MALL size.

	 *  Each chans supports 4MB of MALL so:

	 *

	 *  total_cache_size_in_bytes = max_chans * 4 MB

	 *

	 * - we have avail_chans which shows the number of channels

	 *  we can use if we can't access the entire MALL space.

	 *  It is generally half of max_chans

	 * - so we use the following checks:

	 *

	 *   if (num_chans == max_chans), return max_chans

	 *   if (num_chans < max_chans), return avail_chans

	 *

	 * - exception is GC_11_0_0 where we can't access max_chans,

	 *  so we define max_avail_chans as the maximum available

	 *  MALL space

	 *

	 */

	int gc_11_0_0_max_chans = 48;

	int gc_11_0_0_max_avail_chans = 32;

	int gc_11_0_0_avail_chans = 16;

	int gc_11_0_3_max_chans = 16;

	int gc_11_0_3_avail_chans = 8;

	int gc_11_0_2_max_chans = 8;

	int gc_11_0_2_avail_chans = 4;



	if (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev)) {

		return (num_chans == gc_11_0_0_max_chans) ?

			gc_11_0_0_max_avail_chans : gc_11_0_0_avail_chans;

	} else if (ASICREV_IS_GC_11_0_2(dc->ctx->asic_id.hw_internal_rev)) {

		return (num_chans == gc_11_0_2_max_chans) ?

			gc_11_0_2_max_chans : gc_11_0_2_avail_chans;

	} else { // if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev)) {

		return (num_chans == gc_11_0_3_max_chans) ?

			gc_11_0_3_max_chans : gc_11_0_3_avail_chans;

	}

}

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h

+2 −0
Original line number Diff line number Diff line
@@ -148,6 +148,8 @@ void dcn32_restore_mall_state(struct dc *dc, 


bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe);



unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans);



/* definitions for run time init of reg offsets */



/* CLK SRC */

drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c

+8 −1
Original line number Diff line number Diff line
@@ -1703,11 +1703,18 @@ static bool dcn321_resource_construct( 
	dc->caps.max_cursor_size = 64;

	dc->caps.min_horizontal_blanking_period = 80;

	dc->caps.dmdata_alloc_size = 2048;

	dc->caps.mall_size_per_mem_channel = 0;

	dc->caps.mall_size_per_mem_channel = 4;

	dc->caps.mall_size_total = 0;

	dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;

	dc->caps.cache_line_size = 64;

	dc->caps.cache_num_ways = 16;



	/* Calculate the available MALL space */

	dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(

		dc, dc->ctx->dc_bios->vram_info.num_chans) *

		dc->caps.mall_size_per_mem_channel * 1024 * 1024;

	dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;



	dc->caps.max_cab_allocation_bytes = 33554432; // 32MB = 1024 * 1024 * 32

	dc->caps.subvp_fw_processing_delay_us = 15;

	dc->caps.subvp_drr_max_vblank_margin_us = 40;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+4 −1
Original line number Diff line number Diff line
@@ -2495,8 +2495,11 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa 
		}



		/* Override from VBIOS for num_chan */

		if (dc->ctx->dc_bios->vram_info.num_chans)

		if (dc->ctx->dc_bios->vram_info.num_chans) {

			dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;

			dcn3_2_soc.mall_allocated_for_dcn_mbytes = (double)(dcn32_calc_num_avail_chans_for_mall(dc,

				dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel);

		}



		if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)

			dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

+4 −1
Original line number Diff line number Diff line
@@ -534,8 +534,11 @@ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p 
		}



		/* Override from VBIOS for num_chan */

		if (dc->ctx->dc_bios->vram_info.num_chans)

		if (dc->ctx->dc_bios->vram_info.num_chans) {

			dcn3_21_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;

			dcn3_21_soc.mall_allocated_for_dcn_mbytes = (double)(dcn32_calc_num_avail_chans_for_mall(dc,

				dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel);

		}



		if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)

			dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;