Commit e7d960cd authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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clk: renesas: r9a07g044: Add RSPI clock and reset entries 



Add RSPI{0,1,2} clock and reset entries to CPG driver.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211117002601.17971-1-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent d6dabaf6

drivers/clk/renesas/r9a07g044-cpg.c

+9 −0
Original line number Diff line number Diff line
@@ -246,6 +246,12 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 
				0x588, 0),

	DEF_MOD("sci1",		R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0,

				0x588, 1),

	DEF_MOD("rspi0",	R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0,

				0x590, 0),

	DEF_MOD("rspi1",	R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0,

				0x590, 1),

	DEF_MOD("rspi2",	R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0,

				0x590, 2),

	DEF_MOD("canfd",	R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,

				0x594, 0),

	DEF_MOD("gpio",		R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
@@ -292,6 +298,9 @@ static struct rzg2l_reset r9a07g044_resets[] = { 
	DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),

	DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),

	DEF_RST(R9A07G044_SCI1_RST, 0x888, 1),

	DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0),

	DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1),

	DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2),

	DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),

	DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),

	DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),