Commit d6dabaf6 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV 



Core clock "I" is sourced from CPG_PL1_DDIV divider as per HW manual
Rev.1.00.

This patch adds clock divider table "dtable_1_8" and switches to
DEF_DIV for "I" clock.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211112081003.15453-3-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 86e122c0

drivers/clk/renesas/r9a07g044-cpg.c

+10 −1
Original line number Diff line number Diff line
@@ -56,6 +56,14 @@ enum clk_ids { 
};



/* Divider tables */

static const struct clk_div_table dtable_1_8[] = {

	{0, 1},

	{1, 2},

	{2, 4},

	{3, 8},

	{0, 0},

};



static const struct clk_div_table dtable_1_32[] = {

	{0, 1},

	{1, 2},
@@ -110,7 +118,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 
	DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),



	/* Core output clk */

	DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),

	DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,

		CLK_DIVIDER_HIWORD_MASK),

	DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,

		dtable_1_32, CLK_DIVIDER_HIWORD_MASK),

	DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),