Commit e7540f68 authored by Yazen Ghannam's avatar Yazen Ghannam Committed by PvsNarasimha
Browse files

EDAC/amd64: Remove PCI Function 0 

mainline inclusion
from mainline-v6.3-rc1
commit cf981562
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IAU6ZD

Reference: https://github.com/torvalds/linux/commit/cf981562e6270397a2b0dc871a1f11ccc2a687e8



--------------------------------

commit cf981562 upstream

PCI Function 0 is used on Family 17h and later only to read the "dhar"
value. This value is printed and provided through a module-specific
debug sysfs file. The value is not used for any Family 17h and later
code, and it does not have any apparent debug value on these systems.

Remove "dhar", Function 0 PCI IDs, and all related code.

[Backport changes]

1. Since all the Function 0 PCI IDs have been removed, the macros
PCI_DEVICE_ID_HYGON_18H_M06H_DF_F0 and PCI_DEVICE_ID_HYGON_18H_M10H_DF_F0
have also been removed as per the upstream commit.

Signed-off-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230127170419.1824692-5-yazen.ghannam@amd.com


Signed-off-by: default avatarPvsNarasimha <PVS.NarasimhaRao@amd.com>
parent 999665f4

drivers/edac/amd64_edac.c

+5 −34
Original line number Diff line number Diff line
@@ -1159,9 +1159,6 @@ static void __dump_misc_regs_df(struct amd64_pvt *pvt) 


		debug_display_dimm_sizes_df(pvt, i);

	}



	edac_dbg(1, "F0x104 (DRAM Hole Address): 0x%08x, base: 0x%08x\n",

		 pvt->dhar, dhar_base(pvt));

}



/* Display and decode various NB registers for debug purposes. */
@@ -1196,6 +1193,8 @@ static void __dump_misc_regs(struct amd64_pvt *pvt) 
	/* Only if NOT ganged does dclr1 have valid info */

	if (!dct_ganging_enabled(pvt))

		debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);



	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");

}



/* Display and decode various NB registers for debug purposes. */
@@ -1206,8 +1205,6 @@ static void dump_misc_regs(struct amd64_pvt *pvt) 
	else

		__dump_misc_regs(pvt);



	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");



	amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz);

}
@@ -2643,7 +2640,6 @@ static struct amd64_family_type family_types[] = { 
	},

	[F17_CPUS] = {

		.ctl_name = "F17h",

		.f0_id = PCI_DEVICE_ID_AMD_17H_DF_F0,

		.max_mcs = 2,

		.ops = {

			.early_channel_count	= f17_early_channel_count,
@@ -2652,7 +2648,6 @@ static struct amd64_family_type family_types[] = { 
	},

	[F17_M10H_CPUS] = {

		.ctl_name = "F17h_M10h",

		.f0_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F0,

		.max_mcs = 2,

		.ops = {

			.early_channel_count	= f17_early_channel_count,
@@ -2661,7 +2656,6 @@ static struct amd64_family_type family_types[] = { 
	},

	[F17_M30H_CPUS] = {

		.ctl_name = "F17h_M30h",

		.f0_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F0,

		.max_mcs = 8,

		.ops = {

			.early_channel_count	= f17_early_channel_count,
@@ -2670,7 +2664,6 @@ static struct amd64_family_type family_types[] = { 
	},

	[F17_M60H_CPUS] = {

		.ctl_name = "F17h_M60h",

		.f0_id = PCI_DEVICE_ID_AMD_17H_M60H_DF_F0,

		.max_mcs = 2,

		.ops = {

			.early_channel_count	= f17_early_channel_count,
@@ -2679,7 +2672,6 @@ static struct amd64_family_type family_types[] = { 
	},

	[F17_M70H_CPUS] = {

		.ctl_name = "F17h_M70h",

		.f0_id = PCI_DEVICE_ID_AMD_17H_M70H_DF_F0,

		.max_mcs = 2,

		.ops = {

			.early_channel_count	= f17_early_channel_count,
@@ -2688,7 +2680,6 @@ static struct amd64_family_type family_types[] = { 
	},

	[F18_M06H_CPUS] = {

		.ctl_name = "F18h_M06h",

		.f0_id = PCI_DEVICE_ID_HYGON_18H_M06H_DF_F0,

		.max_mcs = 2,

		.ops = {

			.early_channel_count	= f17_early_channel_count,
@@ -2697,7 +2688,6 @@ static struct amd64_family_type family_types[] = { 
	},

	[F18_M10H_CPUS] = {

		.ctl_name = "F18h_M10h",

		.f0_id = PCI_DEVICE_ID_HYGON_18H_M10H_DF_F0,

		.max_mcs = 2,

		.ops = {

			.early_channel_count	= f17_early_channel_count,
@@ -2706,7 +2696,6 @@ static struct amd64_family_type family_types[] = { 
	},

	[F19_CPUS] = {

		.ctl_name = "F19h",

		.f0_id = PCI_DEVICE_ID_AMD_19H_DF_F0,

		.max_mcs = 8,

		.ops = {

			.early_channel_count	= f17_early_channel_count,
@@ -2715,7 +2704,6 @@ static struct amd64_family_type family_types[] = { 
	},

	[F19_M10H_CPUS] = {

		.ctl_name = "F19h_M10h",

		.f0_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F0,

		.max_mcs = 12,

		.flags.zn_regs_v2 = 1,

		.ops = {
@@ -3046,26 +3034,12 @@ static void decode_umc_error(int node_id, struct mce *m) 
/*

 * Use pvt->F3 which contains the F3 CPU PCI device to get the related

 * F1 (AddrMap) and F2 (Dct) devices. Return negative value on error.

 * Reserve F0 on systems with a UMC.

 */

static int

reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)

{

	if (pvt->umc) {

		pvt->F0 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);

		if (!pvt->F0) {

			amd64_err("F0 not found, device 0x%x (broken BIOS?)\n", pci_id1);

			return -ENODEV;

		}



		if (!pci_ctl_dev)

			pci_ctl_dev = &pvt->F0->dev;



		edac_dbg(1, "F0: %s\n", pci_name(pvt->F0));

		edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));



	if (pvt->umc)

		return 0;

	}



	/* Reserve the ADDRESS MAP Device */

	pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
@@ -3097,7 +3071,7 @@ reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2) 
static void free_mc_sibling_devs(struct amd64_pvt *pvt)

{

	if (pvt->umc) {

		pci_dev_put(pvt->F0);

		return;

	} else {

		pci_dev_put(pvt->F1);

		pci_dev_put(pvt->F2);
@@ -3207,7 +3181,6 @@ static void read_mc_regs(struct amd64_pvt *pvt) 


	if (pvt->umc) {

		__read_mc_regs_df(pvt);

		amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar);



		goto skip;

	}
@@ -3871,8 +3844,6 @@ static int hw_info_get(struct amd64_pvt *pvt) 
		pvt->umc = kcalloc(fam_type->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL);

		if (!pvt->umc)

			return -ENOMEM;



		pci_id1 = fam_type->f0_id;

	} else {

		pci_id1 = fam_type->f1_id;

		pci_id2 = fam_type->f2_id;
@@ -3889,7 +3860,7 @@ static int hw_info_get(struct amd64_pvt *pvt) 


static void hw_info_put(struct amd64_pvt *pvt)

{

	if (pvt->F0 || pvt->F1)

	if (pvt->F1)

		free_mc_sibling_devs(pvt);



	kfree(pvt->umc);

drivers/edac/amd64_edac.h

+2 −12
Original line number Diff line number Diff line
@@ -114,16 +114,6 @@ 
#define PCI_DEVICE_ID_AMD_16H_NB_F2	0x1532

#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581

#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582

#define PCI_DEVICE_ID_AMD_17H_DF_F0	0x1460

#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8

#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490

#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F0 0x1448

#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440

#define PCI_DEVICE_ID_AMD_19H_DF_F0	0x1650

#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F0 0x14ad



#define PCI_DEVICE_ID_HYGON_18H_M06H_DF_F0 0x14b0

#define PCI_DEVICE_ID_HYGON_18H_M10H_DF_F0 0x14d0



/*

 * Function 1 - Address Map
@@ -349,7 +339,7 @@ struct amd64_pvt { 
	struct low_ops *ops;



	/* pci_device handles which we utilize */

	struct pci_dev *F0, *F1, *F2, *F3;

	struct pci_dev *F1, *F2, *F3;



	u16 mc_node_id;		/* MC index of this MC node */

	u8 fam;			/* CPU family */
@@ -504,7 +494,7 @@ struct amd64_family_flags { 


struct amd64_family_type {

	const char *ctl_name;

	u16 f0_id, f1_id, f2_id;

	u16 f1_id, f2_id;

	/* Maximum number of memory controllers per die/node. */

	u8 max_mcs;

	struct amd64_family_flags flags;