Commit 999665f4 authored by Yazen Ghannam's avatar Yazen Ghannam Committed by PvsNarasimha
Browse files

EDAC/amd64: Remove PCI Function 6 

mainline inclusion
from mainline-v6.3-rc1
commit 6229235f
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IAU6ZD

Reference: https://github.com/torvalds/linux/commit/6229235f7c6616c96ac06fd1094520b037410f46



--------------------------------

commit 6229235f upstream

PCI Function 6 is used on Family 17h and later to access scrub
registers. With scrub access removed, this function has no other use.

Remove all Function 6 PCI IDs and related code.

[Backport changes]

1. Since all the Function 6 PCI IDs have been removed, the macros
PCI_DEVICE_ID_HYGON_18H_M06H_DF_F6 and PCI_DEVICE_ID_HYGON_18H_M10H_DF_F6
have also been removed as per the upstream commit.

Signed-off-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230127170419.1824692-4-yazen.ghannam@amd.com


Signed-off-by: default avatarPvsNarasimha <PVS.NarasimhaRao@amd.com>
parent 6bf5571a

drivers/edac/amd64_edac.c

+1 −22
Original line number Diff line number Diff line
@@ -2644,7 +2644,6 @@ static struct amd64_family_type family_types[] = { 
	[F17_CPUS] = {

		.ctl_name = "F17h",

		.f0_id = PCI_DEVICE_ID_AMD_17H_DF_F0,

		.f6_id = PCI_DEVICE_ID_AMD_17H_DF_F6,

		.max_mcs = 2,

		.ops = {

			.early_channel_count	= f17_early_channel_count,
@@ -2654,7 +2653,6 @@ static struct amd64_family_type family_types[] = { 
	[F17_M10H_CPUS] = {

		.ctl_name = "F17h_M10h",

		.f0_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F0,

		.f6_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F6,

		.max_mcs = 2,

		.ops = {

			.early_channel_count	= f17_early_channel_count,
@@ -2664,7 +2662,6 @@ static struct amd64_family_type family_types[] = { 
	[F17_M30H_CPUS] = {

		.ctl_name = "F17h_M30h",

		.f0_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F0,

		.f6_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F6,

		.max_mcs = 8,

		.ops = {

			.early_channel_count	= f17_early_channel_count,
@@ -2674,7 +2671,6 @@ static struct amd64_family_type family_types[] = { 
	[F17_M60H_CPUS] = {

		.ctl_name = "F17h_M60h",

		.f0_id = PCI_DEVICE_ID_AMD_17H_M60H_DF_F0,

		.f6_id = PCI_DEVICE_ID_AMD_17H_M60H_DF_F6,

		.max_mcs = 2,

		.ops = {

			.early_channel_count	= f17_early_channel_count,
@@ -2684,7 +2680,6 @@ static struct amd64_family_type family_types[] = { 
	[F17_M70H_CPUS] = {

		.ctl_name = "F17h_M70h",

		.f0_id = PCI_DEVICE_ID_AMD_17H_M70H_DF_F0,

		.f6_id = PCI_DEVICE_ID_AMD_17H_M70H_DF_F6,

		.max_mcs = 2,

		.ops = {

			.early_channel_count	= f17_early_channel_count,
@@ -2694,7 +2689,6 @@ static struct amd64_family_type family_types[] = { 
	[F18_M06H_CPUS] = {

		.ctl_name = "F18h_M06h",

		.f0_id = PCI_DEVICE_ID_HYGON_18H_M06H_DF_F0,

		.f6_id = PCI_DEVICE_ID_HYGON_18H_M06H_DF_F6,

		.max_mcs = 2,

		.ops = {

			.early_channel_count	= f17_early_channel_count,
@@ -2704,7 +2698,6 @@ static struct amd64_family_type family_types[] = { 
	[F18_M10H_CPUS] = {

		.ctl_name = "F18h_M10h",

		.f0_id = PCI_DEVICE_ID_HYGON_18H_M10H_DF_F0,

		.f6_id = PCI_DEVICE_ID_HYGON_18H_M10H_DF_F6,

		.max_mcs = 2,

		.ops = {

			.early_channel_count	= f17_early_channel_count,
@@ -2714,7 +2707,6 @@ static struct amd64_family_type family_types[] = { 
	[F19_CPUS] = {

		.ctl_name = "F19h",

		.f0_id = PCI_DEVICE_ID_AMD_19H_DF_F0,

		.f6_id = PCI_DEVICE_ID_AMD_19H_DF_F6,

		.max_mcs = 8,

		.ops = {

			.early_channel_count	= f17_early_channel_count,
@@ -2724,7 +2716,6 @@ static struct amd64_family_type family_types[] = { 
	[F19_M10H_CPUS] = {

		.ctl_name = "F19h_M10h",

		.f0_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F0,

		.f6_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F6,

		.max_mcs = 12,

		.flags.zn_regs_v2 = 1,

		.ops = {
@@ -3055,7 +3046,7 @@ static void decode_umc_error(int node_id, struct mce *m) 
/*

 * Use pvt->F3 which contains the F3 CPU PCI device to get the related

 * F1 (AddrMap) and F2 (Dct) devices. Return negative value on error.

 * Reserve F0 and F6 on systems with a UMC.

 * Reserve F0 on systems with a UMC.

 */

static int

reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)
@@ -3067,21 +3058,11 @@ reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2) 
			return -ENODEV;

		}



		pvt->F6 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3);

		if (!pvt->F6) {

			pci_dev_put(pvt->F0);

			pvt->F0 = NULL;



			amd64_err("F6 not found: device 0x%x (broken BIOS?)\n", pci_id2);

			return -ENODEV;

		}



		if (!pci_ctl_dev)

			pci_ctl_dev = &pvt->F0->dev;



		edac_dbg(1, "F0: %s\n", pci_name(pvt->F0));

		edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));

		edac_dbg(1, "F6: %s\n", pci_name(pvt->F6));



		return 0;

	}
@@ -3117,7 +3098,6 @@ static void free_mc_sibling_devs(struct amd64_pvt *pvt) 
{

	if (pvt->umc) {

		pci_dev_put(pvt->F0);

		pci_dev_put(pvt->F6);

	} else {

		pci_dev_put(pvt->F1);

		pci_dev_put(pvt->F2);
@@ -3893,7 +3873,6 @@ static int hw_info_get(struct amd64_pvt *pvt) 
			return -ENOMEM;



		pci_id1 = fam_type->f0_id;

		pci_id2 = fam_type->f6_id;

	} else {

		pci_id1 = fam_type->f1_id;

		pci_id2 = fam_type->f2_id;

drivers/edac/amd64_edac.h

+2 −11
Original line number Diff line number Diff line
@@ -115,24 +115,15 @@ 
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581

#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582

#define PCI_DEVICE_ID_AMD_17H_DF_F0	0x1460

#define PCI_DEVICE_ID_AMD_17H_DF_F6	0x1466

#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8

#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee

#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490

#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496

#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F0 0x1448

#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F6 0x144e

#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440

#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446

#define PCI_DEVICE_ID_AMD_19H_DF_F0	0x1650

#define PCI_DEVICE_ID_AMD_19H_DF_F6	0x1656

#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F0 0x14ad

#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F6 0x14b3



#define PCI_DEVICE_ID_HYGON_18H_M06H_DF_F0 0x14b0

#define PCI_DEVICE_ID_HYGON_18H_M06H_DF_F6 0x14b6

#define PCI_DEVICE_ID_HYGON_18H_M10H_DF_F0 0x14d0

#define PCI_DEVICE_ID_HYGON_18H_M10H_DF_F6 0x14d6



/*

 * Function 1 - Address Map
@@ -358,7 +349,7 @@ struct amd64_pvt { 
	struct low_ops *ops;



	/* pci_device handles which we utilize */

	struct pci_dev *F0, *F1, *F2, *F3, *F6;

	struct pci_dev *F0, *F1, *F2, *F3;



	u16 mc_node_id;		/* MC index of this MC node */

	u8 fam;			/* CPU family */
@@ -513,7 +504,7 @@ struct amd64_family_flags { 


struct amd64_family_type {

	const char *ctl_name;

	u16 f0_id, f1_id, f2_id, f6_id;

	u16 f0_id, f1_id, f2_id;

	/* Maximum number of memory controllers per die/node. */

	u8 max_mcs;

	struct amd64_family_flags flags;