x86/fpu: Set X86_FEATURE_OSXSAVE feature after enabling OSXSAVE in CR4

stable inclusion
from stable-v5.10.193
commit 4bc6a4fca1f06bf4ae1d30e751f52e738c964110
category: bugfix
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8LVBS
CVE: N/A
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=4bc6a4fca1f06bf4ae1d30e751f52e738c964110



-------------------------------------

Intel-SIG: commit 4bc6a4fca1f0 ("x86/fpu: Set X86_FEATURE_OSXSAVE feature after enabling OSXSAVE in CR4")
Backport x86 related patches from 5.10.189 upstream

-------------------------------------

commit 2c66ca39 upstream.

0-Day found a 34.6% regression in stress-ng's 'af-alg' test case, and
bisected it to commit b81fac90 ("x86/fpu: Move FPU initialization into
arch_cpu_finalize_init()"), which optimizes the FPU init order, and moves
the CR4_OSXSAVE enabling into a later place:

   arch_cpu_finalize_init
       identify_boot_cpu
	   identify_cpu
	       generic_identify
                   get_cpu_cap --> setup cpu capability
       ...
       fpu__init_cpu
           fpu__init_cpu_xstate
               cr4_set_bits(X86_CR4_OSXSAVE);

As the FPU is not yet initialized the CPU capability setup fails to set
X86_FEATURE_OSXSAVE. Many security module like 'camellia_aesni_avx_x86_64'
depend on this feature and therefore fail to load, causing the regression.

Cure this by setting X86_FEATURE_OSXSAVE feature right after OSXSAVE
enabling.

[ tglx: Moved it into the actual BSP FPU initialization code and added a comment ]

Fixes: b81fac90 ("x86/fpu: Move FPU initialization into arch_cpu_finalize_init()")
Reported-by: kernel test robot <oliver.sang@intel.com>
Signed-off-by: Feng Tang <feng.tang@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/lkml/202307192135.203ac24e-oliver.sang@intel.com
Link: https://lore.kernel.org/lkml/20230823065747.92257-1-feng.tang@intel.com


Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Aichun Shi <aichun.shi@intel.com>