arm64: perf: Add support for Armv8.1 PMCEID register format

mainline inclusion
from mainline-v4.21-rc1
commit 342e53bd
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I4A1XO
CVE: NA
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=342e53bd8548e07c6a734d2d3a6437ad6e6d3b09



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Armv8.1 allocated the upper 32-bits of the PMCEID registers to describe
the common architectural and microarchitecture events beginning at 0x4000.

Add support for these registers to our probing code, so that we can
advertise the SPE events when they are supported by the CPU.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Qi Liu <liuqi115@huawei.com>
Reviewed-by: Yang Jihong <yangjihong1@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>